Abstract: In a TEDS system, a data transmitting and receiving apparatus is provided and a signal transmitted from a TEDS memory to an apparatus side is logically inverted without using a transformer, and further a sneak signal is prevented. Inverters 28, 30 and zener diodes 32, 34 connected in parallel between the TEDS memory and a data driver of the apparatus are provided. Data transmitted from the TEDS memory to an apparatus 18 side is logically inverted by the inverter 28, and the logical voltage attenuates by a predetermined amount at the zener diode 32 to be supplied to the data driver. Since a sneak signal 100 whose logical voltage attenuates by a predetermined amount again by the zener diode 34 is supplied to the inverter 30, the transmission of a logic value is prevented by setting the threshold of the inverter 30 appropriately.

Abstract: In a TEDS system, a data transmitting and receiving apparatus is provided and a signal transmitted from a TEDS memory to an apparatus side is logically inverted without using a transformer, and further a sneak signal is prevented. Inverters 28, 30 and zener diodes 32, 34 connected in parallel between the TEDS memory and a data driver of the apparatus are provided. Data transmitted from the TEDS memory to an apparatus 18 side is logically inverted by the inverter 28, and the logical voltage attenuates by a predetermined amount at the zener diode 32 to be supplied to the data driver. Since a sneak signal 100 whose logical voltage attenuates by a predetermined amount again by the zener diode 34 is supplied to the inverter 30, the transmission of a logic value is prevented by setting the threshold of the inverter 30 appropriately.

Abstract: A peripheral device reliably reports errors to a main device. When a control signal is received from the main device, an interface circuit requests a voltage detecting circuit to determine whether or not a main circuit section is operative. The voltage detecting circuit determines the capability of operation of the main circuit section based on the state of charge of a charging/discharging section, and outputs the results to the interface circuit. If determined to be operative, the interface circuit turns on a power supply switch to operate the main circuit section, while outputting the control signal received from the main device to the main circuit section. If inoperative, the interface circuit transmits to the main device a signal informing it of the inoperative state.

Abstract: An integrated recorder system includes a recorder main part having a control unit which records instrumental data in a data memory, the control unit and the data memory being interconnected by a shared bus. A plurality of modules are arbitrarily inserted in or withdrawn from the recorder main part, the modules including an input module, the input module having a connector terminal from which an instrumental signal is supplied. A data interface unit is provided in the recorder main part and has a plurality of slots which connect the plurality of modules inserted therein to the data interface unit, the data interface unit being controlled by the control unit through the bus to read the instrumental signal from the input module when inserted in the recorder main part, such that the instrumental data is recorded in the data memory, and controlled by the control unit through the bus to transmit the instrumental data, recorded in the data memory, to an output module when inserted in the recorder main part.

Abstract: A digital audio tape recorder is adapted for recording non-music signals such as, typically, those representative of measurements being made in real time by one or more instruments or meters, together with brief vocal commentary on the measurements and/or with the date and time at which the measurements are made. If the measurements of two instruments or meters are to be recorded simultaneously, the two measurements signals as well as the vocal commentary signal are first digitized. A multiplexing circuit combines the first measurements signal and the commentary signal into a first series of composite data words, and the second measurements signal and a digital time signal into a second series of composite data words. The bits of each composite data word are apportioned between the first measurements signal and the commentary signal, and between the second measurements signal and the time signal, according to their expected relative amounts to be recorded.