Abstract: A processing system and a recording/reproducing system for a digital signal including a digital video signal and a digital audio signal are disclosed. Upon transmission, the digital signal is transmitted after time-base compression and modulation. The transmitted signal is received and demodulated. In the case where the signal is to be transmitted to a plurality of recording/reproducing systems, address signals designating ones of the plural recording/reproducing systems and a control signal for controlling the start/stop of recording are transmitted. The recording by the recording/reproducing system is controlled so that it is made with the same format in either normal-speed or high-speed mode or in either normal or multiple recording mode.

Abstract: The present invention relates to an information providing system. More particularly, this invention relates to an information management apparatus capable of reliable management of distributed information and an information providing system employing the same information management apparatus. The information management apparatus comprises a main information reproducing means for reproducing main information recorded in a given recording medium; and a reproduction management means for managing the main information reproducing means for reproducing the main information. The present invention provides a receiving means provided with a means for recording distributed information and control information limiting the number of main information reproducing cycles on a recording medium, and a main information reproducing means provided with a reproduction disabling means for limiting the reproduction of main information.

Abstract: A product code block generated by adding an outer code block and an inner code block to digital information signal arranged in matrix is received at least twice by a code error correction apparatus. In decoding the first received product code block by use of an inner code parity, an error flag is set for an inner code block having an uncorrectable error by an inner code parity. In decoding the second received product code block by use of an inner code parity, the error flag is referenced so that an inner code block that could be correctly decoded or corrected in the second decoding of all the inner code blocks having an uncorrectable error in the first decoding is replaced by the second inner code block. Also, the check information such as a check sum is generated and stored each time of receiving, and an error flag is set for even an inner code block that could be corrected in either the first or second decoding, if the check sums for them fail to coincide with each other.

Abstract: An information recording and/or reproducing apparatus including a record parity signal adder for receiving error corrected compressed information and an error corrected control signal both of which have been corrected based upon a transmission parity signal added to the compressed information and to the control signal. The record parity signal adder adds a record parity signal to the compressed information which is different from the transmission parity signal. A modulator is provided for modulating the record parity signal added compressed information and a recorder is provided for recording the compressed information modulated by said modulation means. A controller is provided for controlling a start of recording of the recorder based upon the error corrected control signal.

Abstract: A receiving apparatus for receiving a transmitted bit-compressed signal and a transmitted control signal which controls a performance of a recording apparatus. The transmitted bit-compressed signal and the transmitted control signal are transmitted after adding of a parity signal thereto and effecting modulation thereof. The receiving apparatus includes a reception unit for receiving the transmitted bit-compressed signal and the transmitted control signal, a demodulator for demodulating the bit-compressed signal and the control signal outputted by the reception unit in a manner corresponding to the modulation thereof. An error correcting unit receives the demodulated bit-compressed signal and the demodulated control signal for correcting errors therein in accordance with the parity signal added thereto and for at least outputting an error-correcting bit-compressed signal and an error-corrected control signal.

Abstract: A processing system and a recording/reproducing system for a digital signal including a digital video signal and a digital audio signal. Upon transmission, the digital signal is transmitted after time-base compression and modulation. The transmitted signal is received and demodulated. In the case where the signal is to be transmitted to a plurality of recording/reproducing systems, address signals designating ones of the plural recording/reproducing systems and a control signal for controlling the start/stop of recording are transmitted. The recording by the recording/reproducing system is controlled so that it is made with the same format in either normal-speed or high-speed mode or in either normal or multiple recording mode.

Abstract: A digital processing unit for converting a digital picture signal into data by blocks and for correction encoding a variable-length encoded signal. This digital processing unit includes a digital data compressing section for dividing a picture signal into a plurality of number of blocks, and compressingly outputting digital data of this picture signal based on a processing unit of one or a few blocks, a buffer section for sequentially storing the digital data, and an error correction encoding section for sequentially reading the digital data from this buffer section, and structuring an inner code for each inner block structured by this digital data and structuring an outer code for each predetermined unit of inner blocks, to thereby structure two-dimensional error correction code blocks, to output an error correction code signal.

Abstract: A processing system and a recording/reproducing system for a digital signal including a digital video signal and a digital audio signal are disclosed. Upon transmission, the digital signal is transmitted after time-base compression and modulation. The transmitted signal is received and demodulated. In the case where the signal is to be transmitted to a plurality of recording/reproducing systems, address signals designating ones of the plural recording/reproducing systems and a control signal for controlling the start/stop of recording are transmitted. The recording by the recording/reproducing system is controlled so that it is made with the same format in either normal-speed or high-speed mode or in either normal or multiple recording mode.

Abstract: A processing system and a recording/reproducing system for a digital signal including a digital video signal and a digital audio signal are disclosed. Upon transmission, the digital signal is transmitted after time-base compression and modulation. The transmitted signal is received and demodulated. In the case where the signal is to be transmitted to a plurality of recording/reproducing systems, address signals designating ones of the plural recording/reproducing systems and a control signal for controlling the start/stop of recording are transmitted. The recording by the recording/reproducing system is controlled so that it is made with the same format in either normal-speed or high-speed mode or in either normal or multiple recording mode.

Abstract: An information recording-playback apparatus is made up of a circuit for recording first information, which is video data or data for the evaluation of a recording medium such as a magnetic tape, on the first track formed by helical scanning of rotary heads, a circuit for recording second information such as a control signal or time code or third information on a second or third track formed by one or more fixed heads in the longitudinal direction of the tape, and switching device for selecting the operational mode in which the first information and the second or third information are recorded or the operational mode in which only the second or third information is recorded. The arrangement enables pre-formatting of only the second or third information without recording the tape evaluation information.

Abstract: A processing system and a recording/reproducing system for a digital signal including a digital video signal and a digital audio signal. Upon transmission, the digital signal is transmitted after time-base compression and modulation. The transmitted signal is received and demodulated. In the case where the signal is to be transmitted to a plurality of recording/reproducing systems, address signals designating ones of the plural recording/reproducing systems and a control signal for controlling the start/stop of recording are transmitted. The recording by the recording/reproducing system is controlled so that it is made with the same format in either normal-speed or high-speed mode or in either normal or multiple recording mode.

Abstract: A product code block generated by adding an outer code block and an inner code block to digital information signal arranged in matrix is received at least twice by a code error correction apparatus. In decoding the first received product code block by use of an inner code parity, an error flag is set for an inner code block having an uncorrectable error by an inner code parity. In decoding the second received product code block by use of an inner code parity, the error flag is referrenced so that an inner code block that could be correctly decoded or corrected in the second decoding of all the inner code blocks having an uncorrectable error in the first decoding is replaced by the second inner code block. Also, the check information such as a check sum is generated and stored each time of receiving, and an error flag is set for even an inner code block that could be corrected in either the first or second decoding, if the check sums for them fail to coincide with each other.

Abstract: An interpolation circuit, in which a digital signal produced by sampling and quantizing an analog information sequentially is encoded so that, in case a certain one of the encoded sample data is erroneous, a correct data in place of the erroneous sample data is prepared as an interpolation data by interpolating other correct sample data. The interpolation circuit includes: a first extrapolation circuit for generating a first extrapolation data by extrapolating two sample data preceding the erroneous sample data to the position of said erroneous sample data, a second extrapolation circuit for generating a second extrapolation data by extrapolating the two sample data succeeding the erroneous sample data to the position of the erroneous sample data, and an averaging circuit for generating the interpolation data by arithmetically averaging the first and second extrapolation data.

Abstract: A coding device in which N digital signals (time-sequential sampled data), obtained by sampling and quantizing analog video signals, are brought together in one group (N being an integer greater than two) and coded. Among these N sampled data, at least one of them serving as a reference is coded with a number of quantization bits n, which is so great that errors due to the quantization can be neglected, and for the other sampled data the difference between the reference sampled data and each of the others is compressed and coded with a number of bits, which is smaller than n. In this way, even if a coding error is produced; effects thereof are restricted within the gorup where it is produced they are not exerted on the other groups, and thus error propagation does not occur.

Abstract: This invention relates to an error correction upon reproduction of digital signals. The error correction is performed by decoding code words such as cross-interleaved Reed Solomon codes, in which first code blocks are formed by a plurality of information words which are in the first arrangement state and a plurality of first check words which are produced by codes associated with the plurality of information words with a Hamming distance of d.sub.1, and second code blocks are formed by a plurality of information words and a plurality of first check words which are in the second arrangement state and which consist of the said plurality of information words and the said plurality of first check words which are respectively included in the different first code blocks, and by a plurality of second check words which are produced by codes associated with the plurality of information words and the plurality of first check words with a Hamming distance of d.sub.2.

Abstract: A method of transmitting a digital signal in the form of successive signal frames containing codes for detecting and correcting errors of the digital signal for reducing degradation in the quality of the reproduced sound due to generation of the code errors in a digitized audio signal transmission system. An analog signal such as an audio signal is sampled and subjected to A/D conversion. The sample word thus obtained is divided into a plurality of symbol elements. Parity words for detecting and correcting code errors are added to every group of a predetermined number of the information symbols through an interleave procedure before being transmitted.

Abstract: A digital-to-analog converter device for PCM signals at different sampling frequencies comprises a signal converter which expands the frequency distance between a PCM signal band and a side band by converting the sampling frequencies associated with the PCM signals to be reproduced into higher frequencies. With this signal converter, a single low-pass filter can be simplified, having a gradual ramp cut-off characteristic for removal of the side band wherein a pass band cut-off frequency and a stop band cut-off frequency can be adapted for low pass filtering of the PCM signals at different sampling frequencies.

Abstract: An error flag processor for digital signals includes a memory having an information word frame comprised of signal words and correction words, an error detector for detecting errors in an input signal in units of one frame, a write address circuit for writing into an error flag RAM one error flag for one frame upon detection of an error in the words of the frame, an error correcting circuit for correcting data subjected to de-interleave and a read out of the memory, and read address circuit for reading error flags in units of one frame corresponding to individual words from the memory to the error correcting circuit, whereby the storage requirements for the error flags can be reduced. When old storage regions for correction words in the information word frame memory are used as error flag regions and the error flags are arranged in accordance with the signal word frames, the error flag RAM can be omitted.

Abstract: Method and apparatus for detecting and correcting code errors in processing a digital signal such as a digital audio signal are disclosed. An error word correcting parity word generated from a plurality of data words is added to the plurality of data words to form a first frame, and the data words and the parity word of a plurality of different first frames are distributed in a second frame and a plurality of additional parity words for detecting and correcting error words in the second frame are added to the second frame to form a Reed-Solomon code. The code errors are detected and corrected using this code. A code error rate counter is provided, and when an output of the code error counter exceeds a predetermined count, the code error correction is inhibited for a predetermined time period or until the code error rate reaches a second predetermined code error rate.

Abstract: A PCM tape recording and reproducing apparatus for recording and reproducing an audio signal by using multitrack heads, comprises a frame interleaving device with a high dropout immunity function. The frame interleaving device comprises a distributor for successively distributing continuous interleaved input data between tracks, wihtin a multiplicity of tracks formed by splitting a magnetic tape, at a spacing of at least one track so that said continuous interleaved input data will not be shared between two continuous tracks in the same recording and reproducing direction, a data framing circuit for forming a frame out of data to be distributed to each of said tracks and for applying said frame with a synchronization signal at the top of said frame and with an error detection code at the end of said frame, and a delay circuit for delaying data associated with a track by one frame or more with respect to data associated with a neighboring track in the same recording and reproducing as said track.