Patents by Inventor Kejun Zeng

Kejun Zeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9646950
    Abstract: A method for fabricating a semiconductor device is disclosed. A packaged semiconductor device is provided having copper ball bonds attached to aluminum pads. The packaged device is treated for at least one cycle at a temperature in the range from about 250° C. to 270° C. for a period of time in the range from about 20 s to 40 s.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: May 9, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kejun Zeng, Amit Sureshkumar Nangia
  • Publication number: 20160181225
    Abstract: A method for fabricating a semiconductor device is disclosed. A packaged semiconductor device is provided having copper ball bonds attached to aluminum pads. The packaged device is treated for at least one cycle at a temperature in the range from about 250° C. to 270° C. for a period of time in the range from about 20 s to 40 s.
    Type: Application
    Filed: February 2, 2016
    Publication date: June 23, 2016
    Inventors: Kejun Zeng, Amit Sureshkumar Nangia
  • Publication number: 20120001336
    Abstract: A connection formed by a copper wire (112) alloyed with a noble metal in a first concentration bonded to a terminal pad (101) of a semiconductor chip; the end of the wire being covered with a zone (302) including an alloy of copper and the noble metal in a second concentration higher than the first concentration. When the noble metal is gold, the first concentration may range from about 0.5 to 2.0 weight %, and the second concentration from about 1.0 to 5.0 weight %. The zone of the alloy of the second concentration may have a thickness from about 20 to 50 nm.
    Type: Application
    Filed: July 2, 2010
    Publication date: January 5, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kejun ZENG, Wei Qun PENG
  • Publication number: 20110177686
    Abstract: A metallic interconnect structure (200) for connecting a gold bump (205) and a contact pad (212), as used for example in semiconductor flip-chip assembly. A first region (207) of binary AuSn2 intermetallic is adjacent to the gold bump. A region (208) of binary AuSn4 intermetallic is adjacent to the first AuSn2 region. Then, a region (209) of binary gold-tin solid solution is adjacent to the AuSn4 region, and a second region (210) of binary AuSn2 intermetallic is adjacent to the solid solution region. The second AuSn2 region is adjacent to a nickel layer (213) (preferred thickness about 0.08 ?m), which covers the copper pad. The nickel layer insures that the gold/tin intermetallics and solutions remain substantially free of copper and thus avoid ternary compounds, providing stabilized gold bump/solder connections.
    Type: Application
    Filed: March 29, 2011
    Publication date: July 21, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kejun ZENG, Wei Qun PENG, Rebecca L. HOLFORD, Robert John FURTAW, Bernardo GALLEGOS
  • Publication number: 20110108980
    Abstract: A metallic interconnect structure (200) for connecting a gold bump (205) and a copper pad (212), as used for example in semiconductor flip-chip assembly. A first region (207) of binary AuSn2 intermetallic is adjacent to the gold bump. A region (208) of binary AuSn4 intermetallic is adjacent to the first AuSn2 region. Then, a region (209) of binary gold-tin solid solution is adjacent to the AuSn4 region, and a second region (210) of binary AuSn2 intermetallic is adjacent to the solid solution region. The second AuSn2 region is adjacent to a nickel layer (213) (preferred thickness about 0.08 ?m), which covers the copper pad. The nickel layer insures that the gold/tin intermetallics and solutions remain substantially free of copper and thus avoid ternary compounds, providing stabilized gold bump/solder connections.
    Type: Application
    Filed: October 4, 2007
    Publication date: May 12, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kejun Zeng, Wei Qun Peng, Rebecca L. Holford, Robert John Furtaw, Bernardo Gallegos
  • Patent number: 7939939
    Abstract: A metallic interconnect structure (200) for connecting a gold bump (205) and a copper pad (212), as used for example in semiconductor flip-chip assembly. A first region (207) of binary AuSn2 intermetallic is adjacent to the gold bump. A region (208) of binary AuSn4 intermetallic is adjacent to the first AuSn2 region. Then, a region (209) of binary gold-tin solid solution is adjacent to the AuSn4 region, and a second region (210) of binary AuSn2 intermetallic is adjacent to the solid solution region. The second AuSn2 region is adjacent to a nickel layer (213) (preferred thickness about 0.08 ?m), which covers the copper pad. The nickel layer insures that the gold/tin intermetallics and solutions remain substantially free of copper and thus avoid ternary compounds, providing stabilized gold bump/solder connections.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: May 10, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Kejun Zeng, Wei Qun Peng, Rebecca L. Holford, Robert John Furtaw, Bernardo Gallegos
  • Publication number: 20100219528
    Abstract: A semiconductor device contact structure practically eliminating the copper diffusion into the solder as well as the current crowding at the contact with the subsequent electromigration in the solder. A column-like electroplated copper stud (108) is on each contact pad. The stud is sized to provide low, uniform electrical resistance in order to spread the current from the contact to an approximately uniform, low density. Preferably, the stud height (108a) is at least ten times the thickness of the copper interconnect layer (104). Stud (108) is capped by an electroplated nickel layer (109) thick enough (preferably about 2 ?m) to suppress copper diffusion from stud (108) into solder body (120), thus practically inhibiting intermetallic compound formation and Kirkendall voiding.
    Type: Application
    Filed: May 12, 2010
    Publication date: September 2, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jie-Hua ZHAO, Vikas GUPTA, Kejun ZENG
  • Publication number: 20090297879
    Abstract: A solder joint (200) has a first contact pad 114 and a second contact pad 124 of a first metal, preferably copper, facing each other across a gap. A coat and 125, respectively) of a second metal, preferably nickel, covers each pad. A layer 201 of crystals of first intermetallic compounds, such as Ni3Sn4 and (Ni, Cu)3Sn4, covers the surface of each coat. Isolated crystals 202 of second intermetallic compounds, such as Cu6Sn5 and (Cu, Ni)6Sn5, different from the first intermetallic compounds, are dispersed on top of the layer 201 of crystals of the first intermetallic compounds. A solder alloy 203 including a third metal, preferably tin, and the first metal fills the gap. The solder alloy 203 may further include a fourth metal, preferably selected from a group of metals including silver, zinc, and indium.
    Type: Application
    Filed: May 11, 2009
    Publication date: December 3, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kejun ZENG, Rajiv DUNNE, Masood MURTUZA
  • Publication number: 20090091024
    Abstract: A metallic interconnect structure (200) for connecting a gold bump (205) and a copper pad (212), as used for example in semiconductor flip-chip assembly. A first region (207) of binary AuSn2 intermetallic is adjacent to the gold bump. A region (208) of binary AuSn4 intermetallic is adjacent to the first AuSn2 region. Then, a region (209) of binary gold-tin solid solution is adjacent to the AuSn4 region, and a second region (210) of binary AuSn2 intermetallic is adjacent to the solid solution region. The second AuSn2 region is adjacent to a nickel layer (213) (preferred thickness about 0.08 ?m), which covers the copper pad. The nickel layer insures that the gold/tin intermetallics and solutions remain substantially free of copper and thus avoid ternary compounds, providing stabilized gold bump/solder connections.
    Type: Application
    Filed: October 4, 2007
    Publication date: April 9, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kejun Zeng, Wei Qun Peng, Rebecca L. Holford, Robert John Furtaw, Bernardo Gallegos
  • Publication number: 20080251927
    Abstract: A semiconductor device contact structure practically eliminating the copper diffusion into the solder as well as the current crowding at the contact with the subsequent electromigration in the solder. A column-like electroplated copper stud (108) is on each contact pad. The stud is sized to provide low, uniform electrical resistance in order to spread the current from the contact to an approximately uniform, low density. Preferably, the stud height (108a) is at least ten times the thickness of the copper interconnect layer (104). Stud (108) is capped by an electroplated nickel layer (109) thick enough (preferably about 2 ?m) to suppress copper diffusion from stud (108) into solder body (120), thus practically inhibiting intermetallic compound formation and Kirkendall voiding.
    Type: Application
    Filed: July 9, 2007
    Publication date: October 16, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jie-Hua Zhao, Vikas Gupta, Kejun Zeng
  • Publication number: 20080083993
    Abstract: A metal interconnection for two workplaces such as a semiconductor chip and an insulating substrate. The first workpiece (101) has a first contact pad (201) with a gold stud (110); the second workplace (103) is covered with an insulating layer (213) and a window in the layer to a second contact pad (211). The interconnection between the second pad and the gold stud is a 278° C. eutectic structure (111) with about 80 weight percent gold and about 20 weight percent tin. The eutectic structure has a Young's modulus of 59.2 GPa and a lamellar micro-structure of the phases Au5Sn and AuSn. There is substantially no metallic tin at the second contact pad.
    Type: Application
    Filed: June 19, 2007
    Publication date: April 10, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kejun Zeng, Donald Abbott, Wei Qun Peng
  • Patent number: 7291549
    Abstract: A method for reducing gold embrittlement in solder joints, and a copper-bearing solder according to the method, are disclosed. Embodiments of the invention comprise adding copper to non-copper based solder, such as tin-lead solder. The embodiments may further comprise using the copper-bearing solder as a solder interconnect on a gold-nickel pad.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: November 6, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Kejun Zeng
  • Patent number: 7267861
    Abstract: A metal interconnect structure (100) comprising a bond pad (101), which has copper with at least 70 volume percent composed of crystal grains expanding more than 1 ?m in their main direction, and 30 or less volume percent composed of crystal grains, which expand less than 1 ?m in their main crystal direction. A body (102) of tin alloy is in contact with the bond pad.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: September 11, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Darvin R. Edwards, Tz-Cheng Chiu, Kejun Zeng
  • Publication number: 20060267157
    Abstract: A metal interconnect structure (100) comprising a bond pad (101), which has copper with at least 70 volume percent composed of crystal grains expanding more than 1 ?m in their main direction, and 30 or less volume percent composed of crystal grains, which expand less than 1 ?m in their main crystal direction. A body (102) of tin alloy is in contact with the bond pad.
    Type: Application
    Filed: May 31, 2005
    Publication date: November 30, 2006
    Inventors: Darvin Edwards, Tz-Cheng Chiu, Kejun Zeng
  • Patent number: 7070088
    Abstract: Method for assembling a semiconductor device having fatigue-resistant interconnection fillet provides a semiconductor chip with at least one solder bump comprising an alloy of tin and lead with a melting temperature higher than the solder paste used. Further, a solder paste (preferably binary) is provided, which comprises tin and about 2.5 weight percent silver, and has a melting temperature of about 221° C. The solder bump is brought in contact with the solder paste, the bump is partially immersed in the paste, and thermal energy is supplied to reflow the solder paste at about 235° C. The amount of energy and time after the reflow of the paste is controlled so that the molten paste dissolves a pre-determined amount of the solder bump (lead and tin) to form a ternary alloy of about eutectic composition (about 1.62 weight % Ag, 36.95 weight % Pb, 61.43 weight % Sn) without melting the solder bump.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: July 4, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Kejun Zeng
  • Publication number: 20060097398
    Abstract: A method for reducing gold embrittlement in solder joints, and a copper-bearing solder according to the method, are disclosed. Embodiments of the invention comprise adding copper to non-copper based solder, such as tin-lead solder. The embodiments may further comprise using the copper-bearing solder as a solder interconnect on a gold-nickel pad.
    Type: Application
    Filed: December 13, 2005
    Publication date: May 11, 2006
    Inventor: Kejun Zeng
  • Patent number: 7005745
    Abstract: A method for reducing gold embrittlement in solder joints, and a copper-bearing solder according to the method, are disclosed. Embodiments of the invention comprise adding copper to non-copper based solder, such as tin-lead solder. The embodiments may further comprise using the copper-bearing solder as a solder interconnect on a gold-nickel pad.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: February 28, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Kejun Zeng
  • Publication number: 20060038302
    Abstract: A solder comprising a ternary alloy of tin, lead, and silver, providing approximately the eutectic melting temperature and about 0.7 to 1.5 weight percent silver. In one embodiment, the ternary solder alloy comprises the composition of about 61.0 weight percent tin, about 37.5 weight percent lead, and about 1.5 percent weight percent silver. In another embodiment, the ternary solder alloy comprises the composition of about 61.3 weight percent tin, about 37.7 weight percent lead, and about 1.0 percent weight percent silver. At these silver concentrations, precipitated Ag3Sn particles (210), embedded in the matrix of the eutectic alloy (201), can pin down (222) moving dislocations (220) and thus increase the fatigue resistance of the solder.
    Type: Application
    Filed: August 19, 2004
    Publication date: February 23, 2006
    Inventor: Kejun Zeng
  • Publication number: 20050275096
    Abstract: A metal interconnect structure (100) comprising a bond pad (110) of copper; a body (103) of eutectic alloy in contact with the bond pad, this alloy including copper; and a contact pad (120) comprising copper in contact with the alloy body. When the eutectic alloy is tin/lead, the alloy includes copper in an amount greater than 0.08 weight percent and less than 2.0 weight percent. When the eutectic alloy is tin/silver, the alloy includes copper in an amount greater than 0.9 weight percent and less than 2.0 weight percent.
    Type: Application
    Filed: August 16, 2004
    Publication date: December 15, 2005
    Inventors: Kejun Zeng, Tz-Cheng Chiu, Rebecca Holdford
  • Publication number: 20050199684
    Abstract: Method for assembling a semiconductor device having fatigue-resistant interconnection fillet provides a semiconductor chip with at least one solder bump comprising an alloy of tin and lead with a melting temperature higher than the solder paste used. Further, a solder paste (preferably binary) is provided, which comprises tin and about 2.5 weight percent silver, and has a melting temperature of about 221° C. The solder bump is brought in contact with the solder paste, the bump is partially immersed in the paste, and thermal energy is supplied to reflow the solder paste at about 235° C. The amount of energy and time after the reflow of the paste is controlled so that the molten paste dissolves a pre-determined amount of the solder bump (lead and tin) to form a ternary alloy of about eutectic composition (about 1.62 weight % Ag, 36.95 weight % Pb, 61.43 weight % Sn) without melting the solder bump.
    Type: Application
    Filed: March 9, 2004
    Publication date: September 15, 2005
    Inventor: Kejun Zeng