Abstract: An array substrate includes a slit electrode and a planar electrode disposed in each of sub-pixels on a base substrate. The planar electrode is located on a side of the slit electrode close to the base substrate, and the slit electrode includes a plurality of strip sub-electrodes. In each of the sub-pixels, an insulating layer is disposed between the slit electrode and the planar electrode, and a surface of the insulating layer facing away from the base substrate is provided with a groove at a position between at least one set of adjacent strip sub-electrodes in the plurality of strip sub-electrodes.

Abstract: An array substrate and a display device including the array substrate are provided. The array substrate includes: an upper electrode layer on a base substrate and including a first upper electrode strip and a second upper electrode strip; a lower electrode layer between the base substrate and the upper electrode layer. The lower electrode layer includes a portion that does not overlap the first upper electrode strip and the second upper electrode strip in a direction perpendicular to an upper surface of the base substrate. The array substrate includes a pixel electrode strip and a common electrode strip which are in a same layer and both correspond to a region between the first upper electrode strip and the second upper electrode strip.

Abstract: An array substrate, a method for manufacturing the same, a liquid crystal display panel, and a display device are provided. The array substrate includes a first substrate, signal lines and an insulating layer; the insulating layer is disposed on the first substrate, and grooves are disposed on a side of the insulating layer facing away from the first substrate and disposed in a region of the insulating layer corresponding to a non-display region of the array substrate; and the signal lines are disposed on inner walls of the grooves, a direction of the inner walls of the grooves is arranged such that at least a portion of light incident on the signal lines from a side of the first substrate facing away from the signal lines is reflected to a display region of the array substrate.

Abstract: An array substrate and a display device including the array substrate are provided. The array substrate includes: an upper electrode layer on a base substrate and including a first upper electrode strip and a second upper electrode strip; a lower electrode layer between the base substrate and the upper electrode layer. The lower electrode layer includes a portion that does not overlap the first upper electrode strip and the second upper electrode strip in a direction perpendicular to an upper surface of the base substrate. The array substrate includes a pixel electrode strip and a common electrode strip which are in a same layer and both correspond to a region between the first upper electrode strip and the second upper electrode strip.

Abstract: A thin film transistor includes a gate, an active layer, a source, a drain. The source includes a connecting portion, a first sub-portion, a second sub-portion, and a third sub-portion that are arranged sequentially and in parallel. At first ends of the sub-portions, the connecting portion is connected to the portions to form two adjacent recesses. At second ends of the sub-portions, the distance from an end of the second sub-portion to the connecting portion is smaller than a distance from an end of the first sub-portion to the connecting portion and a distance from an end of the third sub-portion to the connecting portion. The drain includes a connecting block, a first drain and a second drain disposed in the two recesses respectively, and at least a portion of the connecting block is disposed between the first and the second drains to connect the first and the second drains.

Abstract: An array substrate, a method for manufacturing the same, a liquid crystal display panel, and a display device are provided. The array substrate includes a first substrate; signal lines and an insulating layer; the insulating layer is disposed on the first substrate, and grooves are disposed on a side of the insulating layer facing away from the first substrate and disposed in a region of the insulating layer corresponding to a non-display region of the arm substrate; and the signal lines are disposed on inner walls of the grooves, a direction of the inner walls of the grooves is arranged such that at least a portion of light incident on the signal lines from a side of the first substrate facing away from the signal lines is reflected to a display region of the array substrate.

Abstract: Disclosure are an array substrate, a display panel and a display device. The array substrate includes a base substrate and a plurality of pixel units disposed on the base substrate. Each of the pixel units includes a first subpixel unit and a second subpixel unit; the first subpixel unit includes a first pixel electrode and a first common electrode; the second subpixel unit includes a second pixel electrode and a second common electrode which are insulated from each other; the first pixel electrode is electrically connected with the second pixel electrode; and the stacking sequence of the first pixel electrodes and the first common electrodes in the direction perpendicular to the base substrate is opposite to the stacking sequence of the second pixel electrodes and the second common electrodes in the direction perpendicular to the base substrate. The array substrate can effectively improve poor quality such as afterimage.

Abstract: The disclosure discloses an array substrate, a display panel and a display device. The array substrate includes a peripheral circuit area in which a plurality of first wire grooves, a plurality of second wire grooves, a plurality of first lead wires and a plurality of second lead wires are arranged, wherein each first lead wire is arranged corresponding to one of the first wire grooves, and laid out on a bottom and sidewalls of a corresponding first wire groove; and each second lead wire is arranged corresponding to one of the second wire grooves, and a plurality of recesses and protrusions are arranged alternately on a bottom surface of each second wire groove along an extension direction of the each second wire groove, wherein each second lead wire is laid out on surfaces of recesses and protrusions on a bottom surface of a corresponding second wire groove.

Abstract: A TFT array substrate, its manufacturing method and a corresponding display device are disclosed. The TFT array substrate, includes a bearing substrate, a gate line and a data line arranged across each other on the bearing substrate, a pixel region defined by the gate line and the data line, and a thin film transistor, a pixel electrode and an active layer disposed in the pixel region. Specifically, a gate of the thin film transistor is connected to the gate line, a source thereof is connected to the data line and a drain thereof is connected to the pixel electrode. Further, an insulating layer is also formed above the source of the thin film transistor, and a drain trench is formed in the insulating layer. In addition, the drain of the thin film transistor is in the drain trench and is connected to the source through the active layer.

Abstract: A thin film transistor includes a gate, an active layer, a source, a drain. The source includes a connecting portion, a first sub-portion, a second sub-portion, and a third sub-portion that are arranged sequentially and in parallel. At first ends of the sub-portions, the connecting portion is connected to the portions to form two adjacent recesses. At second ends of the sub-portions, the distance from an end of the second sub-portion to the connecting portion is smaller than a distance from an end of the first sub-portion to the connecting portion and a distance from an end of the third sub-portion to the connecting portion. The drain includes a connecting block, a first drain and a second drain disposed in the two recesses respectively, and at least a portion of the connecting block is disposed between the first and the second drains to connect the first and the second drains.

Abstract: A TFT and a method for manufacturing the same, an array substrate and a display device are provided. The TFT includes a first electrode pattern and a second electrode pattern arranged at an identical layer. The first electrode pattern includes a first strip-like portion extending in a first direction, and the second electrode pattern includes a bending portion surrounding a first end of the first strip-like portion. The second electrode pattern further includes a second strip-like portion extending from a first end of the bending portion in the first direction. A channel formation region of the TFT includes a region between the bending portion and the first strip-like portion, and a region between the second strip-like portion and the first strip-like portion.

Abstract: It is provided a grayscale voltage debugging method for debugging a display device including a white subpixel, including a first step of, in a state where the white subpixel is disenabled and subpixels in other colors are enabled, adjusting a respective to-be-adjusted grayscale voltage applied to each of the subpixels in other colors, so that a first actually-measured Gamma curve corresponding to the respective adjusted grayscale voltage is located within an acceptable range of a standard Gamma curve, and a second step of, in a state where the white subpixel and the subpixels in other colors are all enabled, acquiring a second actually-measured Gamma curve and in the case that the second actually-measured Gamma curve is not located within the acceptable range, changing the respective adjusted grayscale voltage to obtain a new respective to-be-adjusted grayscale voltage, and returning to the first step.

Abstract: The disclosure discloses an array substrate, a display panel and a display device. The array substrate includes a peripheral circuit area in which a plurality of first wire grooves, a plurality of second wire grooves, a plurality of first lead wires and a plurality of second lead wires are arranged, wherein each first lead wire is arranged corresponding to one of the first wire grooves, and laid out on a bottom and sidewalls of a corresponding first wire groove; and each second lead wire is arranged corresponding to one of the second wire grooves, and a plurality of recesses and protrusions are arranged alternately on a bottom surface of each second wire groove along an extension direction of the each second wire groove, wherein each second lead wire is laid out on surfaces of recesses and protrusions on a bottom surface of a corresponding second wire groove.

Abstract: It is provided a grayscale voltage debugging method for debugging a display device including a white subpixel, including a first step of, in a state where the white subpixel is disenabled and subpixels in other colors are enabled, adjusting a respective to-be-adjusted grayscale voltage applied to each of the subpixels in other colors, so that a first actually-measured Gamma curve corresponding to the respective adjusted grayscale voltage is located within an acceptable range of a standard Gamma curve, and a second step of, in a state where the white subpixel and the subpixels in other colors are all enabled, acquiring a second actually-measured Gamma curve and in the case that the second actually-measured Gamma curve is not located within the acceptable range, changing the respective adjusted grayscale voltage to obtain a new respective to-be-adjusted grayscale voltage, and returning to the first step.

Abstract: The present application discloses a display panel having a plurality of gate lines and a gate driving circuit for driving the plurality of gate lines, the gate driving circuit including a plurality of first cascaded shift register units and a plurality of second cascaded shift register units for applying gate scanning signals to gate lines connected thereto.

Abstract: A TFT and a method for manufacturing the same, an array substrate and a display device are provided. The TFT includes a first electrode pattern and a second electrode pattern arranged at an identical layer. The first electrode pattern includes a first strip-like portion extending in a first direction, and the second electrode pattern includes a bending portion surrounding a first end of the first strip-like portion. The second electrode pattern further includes a second strip-like portion extending from a first end of the bending portion in the first direction. A channel formation region of the TFT includes a region between the bending portion and the first strip-like portion, and a region between the second strip-like portion and the first strip-like portion.

Abstract: A TFT array substrate, its manufacturing method and a corresponding display device are disclosed. The TFT array substrate, includes a bearing substrate, a gate line and a data line arranged across each other on the bearing substrate, a pixel region defined by the gate line and the data line, and a thin film transistor, a pixel electrode and an active layer disposed in the pixel region. Specifically, a gate of the thin film transistor is connected to the gate line, a source thereof is connected to the data line and a drain thereof is connected to the pixel electrode. Further, an insulating layer is also formed above the source of the thin film transistor, and a drain trench is formed in the insulating layer. In addition, the drain of the thin film transistor is in the drain trench and is connected to the source through the active layer.

Abstract: The present application discloses a display panel having a plurality of gate lines and a gate driving circuit for driving the plurality of gate lines, the gate driving circuit including a plurality of first cascaded shift register units and a plurality of second cascaded shift register units for applying gate scanning signals to gate lines connected thereto.