Abstract: A control method and apparatus for displaying multimedia content, an electronic device, and a medium. The method includes: displaying a first-type multimedia content on a first content display layer of a first-type multimedia content display interface, the first-type multimedia content display interface including: a first user interaction layer and the first content display layer, the first user interaction layer being superimposed and displayed on the first content display layer; and receiving a first swiping operation inputted by a user on the user interaction layer, and exiting the first-type multimedia content display interface. That is, a swiping operation triggers to exit the first-type multimedia content display interface, as the swiping operation is significantly different from a click operation, the user is provided with a multimedia content display control method that is more consistent with the user's operation habit, improving the user experience.

Abstract: A nonvolatile resistive switching memory, comprising an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode, and characterized in that: a graphene barrier layer is inserted between the inert metal electrode and the resistive switching functional layer, which is capable of preventing the easily oxidizable metal ions from migrating into the inert metal electrode through the resistive switching functional layer under the action of electric field during the programming of the device.

Abstract: A nonvolatile resistive switching memory, comprising an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode, and characterized in that: a graphene barrier layer is inserted between the inert metal electrode and the resistive switching functional layer, which is capable of preventing the easily oxidizable metal ions from migrating into the inert metal electrode through the resistive switching functional layer under the action of electric field during the programming of the device.

Abstract: A method of fabricating an asymmetric FinFET is provided in the invention, comprising: a. providing a substrate (101); b. forming a fin (102) on the substrate (101), wherein the width of the fin (102) is defined as a second channel thickness; c. forming a shallow trench isolation; d. forming a sacrificial gate stack on the top surface and sidewalls of the channel which is in the middle of the fin, and forming source/drain regions in both ends of the fin; e. depositing an interlayer dielectric layer to cover the sacrificial gate stack and the source/drain regions, planarizing the interlayer dielectric layer to expose sacrificial gate stack; f. removing the sacrificial gate stack to expose the channel; g. forming an etch-stop layer (106) on top of the channel; h. covering a photoresist film (400) on a portion of the semiconductor structure near the source region; i.

Abstract: The present invention provides a method for manufacturing a semiconductor device, comprising: forming a contact sacrificial pattern on a substrate to cover source and drain regions and expose a gate region; forming an interlayer dielectric layer on the substrate to cover the contact sacrificial pattern and expose the gate region; forming a gate stack structure in the exposed gate region; removing the contact sacrificial pattern to form the source/drain contact trench; and forming a source/drain contact in the source/drain contact trench. By means of a contact sacrificial layer process, the method of manufacturing a semiconductor device according to the present invention effectively reduces the distance between the gate spacer and the contact region and increases the area of the contact region, thus effectively reducing the parasitic resistance of the device.

Abstract: A method of manufacturing a FinFET device is provided, comprising: a. providing a substrate (100); b. forming a fin (200) on the substrate; c. forming an shallow trench isolation structure (300) on the substrate; d. forming an sacrificial gate stack on the isolation structure, wherein the sacrificial gate stack intersects the fin; e. forming source/drain doping regions by ion implantation into the fin; f. depositing an interlayer dielectric layer (400) on the substrate; g. removing the sacrificial gate stack to form a sacrificial gate vacancy; h. forming an doped region (201) under the sacrificial gate vacancy; i. etching the shallow trench isolation structure (300) under the sacrificial gate vacancy until the top surface of the shallow trench isolation structure (300) levels with the bottom surface of the source/drain doping regions; j. forming a new gate stack in the sacrificial gate vacancy.

Abstract: A method for manufacturing a semiconductor device is disclosed. The method comprises: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; forming a T-shape metal gate structure by filling a metal layer in the T-shape gate trench. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a dummy gate stack structure on a substrate, wherein the dummy gate stack structure contains carbon-based materials; forming source/drain region in the substrate on both sides of the dummy gate stack structure; performing etching to remove the dummy gate stack structure until the substrate is exposed, resulting in a gate trench; and forming a gate stack structure in the gate trench. In accordance with the method for manufacturing a semiconductor device of the present invention, the dummy gate made of carbon-based materials is used to substitute the dummy gate made of silicon-based materials, then no oxide liner and/or etch blocking layer needs be added while the dummy gate is removed by etching in the gate last process, thus the reliability of device is ensured while the process is simplified and the cost is reduced.

Abstract: A method of manufacturing a FinFET device is provided, comprising: a. providing a substrate (100); b. forming a fin (200) on the substrate; c. forming an shallow trench isolation structure (300) on the substrate; d. forming an sacrificial gate stack on the isolation structure, wherein the sacrificial gate stack intersects the fin; e. forming source/drain doping regions by ion implantation into the fin; f. depositing an interlayer dielectric layer (400) on the substrate; g. removing the sacrificial gate stack to form a sacrificial gate vacancy; h. forming an doped region (201) under the sacrificial gate vacancy; i. etching the shallow trench isolation structure (300) under the sacrificial gate vacancy until the top surface of the shallow trench isolation structure (300) levels with the bottom surface of the source/drain doping regions; j. forming a new gate stack in the sacrificial gate vacancy.

Abstract: A method for manufacturing an asymmetric super-thin SOIMOS transistor is disclosed. The method comprises: a. providing a substrate composed of an insulating layer (200) and a semiconductor layer (300); b. forming a gate stack (304) on the substrate; c. removing semiconductor materials of the semiconductor layer (300) on a source region side to form a first vacancy (001); d. removing insulating materials of the insulating layer (200) in the source region and under channel near the source region to form a second vacancy (002); e. filling semiconductor materials into the first vacancy (001) and the second vacancy (002) to connect with the semiconductor materials above the second vacancy (002); and f. performing source/drain implantation. Compared with the prior art, the method of the disclosure can suppress the short channel effects and enhance device performance.

Abstract: A method of fabricating an asymmetric FinFET is provided in the invention, comprising: a. providing a substrate (101); b. forming a fin (102) on the substrate (101), wherein the width of the fin (102) is defined as a second channel thickness; c. forming a shallow trench isolation; d. forming a sacrificial gate stack on the top surface and sidewalls of the channel which is in the middle of the fin, and forming source/drain regions in both ends of the fin; e. depositing an interlayer dielectric layer to cover the sacrificial gate stack and the source/drain regions, planarizing the interlayer dielectric layer to expose sacrificial gate stack; f. removing the sacrificial gate stack to expose the channel; g. forming an etch-stop layer (106) on top of the channel; h. covering a photoresist film (400) on a portion of the semiconductor structure near the source region; i.

Abstract: A method for fabricating a FinFET DEVICE is provided in the invention, comprising: a. providing a substrate (100);b. forming a fin (200) on the substrate (200); c. depositing a doping material layer (300) on the semiconductor structure formed after the step b; d. forming a first shallow trench isolation (400) on the semiconductor formed after the step c; e. removing a portion of the doping material layer (300) which is not covered by the first shallow trench isolation (400); f. performing an annealing process to form a doped region (500) in a channel region which is in the middle portion of the fin; g. forming a second shallow trench isolation (600) on the semiconductor formed after the step f; h. forming a source region and a drain region in opposite portions of the fin and forming a gate stack on the middle portion of the fin. Comparing with the prior art, punch through effect will be restrained and process complexity will be reduced.

Abstract: A method for manufacturing a semiconductor device is disclosed. The method comprises: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; forming a T-shape metal gate structure by filling a metal layer in the T-shape gate trench. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.

Abstract: The present invention provides a method for manufacturing a shallow trench isolation, comprising: forming a hard mask layer on the substrate; phottoetching/etching the hard mask layer and the substrate to form a plurality of first trenches along a first direction and a plurality of second trenches along a second direction perpendicular to the first direction, wherein the volume of the second trench is greater than that of the first trench; depositing an insulating material in the first and second trenches; planarizing the insulating material and the hard mask layer until the substrate is exposed so as to form a shallow trench isolation.

Abstract: The present invention provides a method for manufacturing a semiconductor device, comprising: forming a contact sacrificial pattern on a substrate to cover source and drain regions and expose a gate region; forming an interlayer dielectric layer on the substrate to cover the contact sacrificial pattern and expose the gate region; forming a gate stack structure in the exposed gate region; removing the contact sacrificial pattern to form the source/drain contact trench; and forming a source/drain contact in the source/drain contact trench. By means of a contact sacrificial layer process, the method of manufacturing a semiconductor device according to the present invention effectively reduces the distance between the gate spacer and the contact region and increases the area of the contact region, thus effectively reducing the parasitic resistance of the device.

Abstract: A method for manufacturing a semiconductor device, comprising: forming a gate stack structure and gate spacers on the substrate; forming the raised S/D regions on the substrate on both sides of the gate stack structure and the gate spacers; depositing a lower interlayer dielectric layer on the entire device, and planarizing the lower interlayer dielectric layer and the gate stack structure until the raised S/D regions are exposed; selective epitaxial growing to form the S/D extension regions in the raised S/D regions; forming an upper interlayer dielectric layer on the S/D extension regions; etching the upper interlayer dielectric layer until the S/D extension regions to form an S/D contact hole; forming a metal silicide in the S/D contact hole.

Abstract: A method for manufacturing a semiconductor device is disclosed, comprising: forming a contact sacrificial layer on the substrate, etching the contact sacrificial layer to form a contact sacrificial pattern, wherein the contact sacrificial pattern covers the source region and the drain region and has a gate trench that exposes the substrate; forming a gate spacer and a gate stack structure in the gate trench; partially or completely etching off the contact sacrificial pattern that covers the source region and the drain region so as to form a source/drain contact trench; and forming a source/drain contact in the source/drain contact trench. By means of the double-layer contact sacrificial layer, the method for manufacturing a semiconductor device in accordance with the present invention effectively reduces the spacing between the gate spacer and the contact region and increases the area of contact region, thus effectively reducing the parasitic resistance of the device.

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a dummy gate stack structure on a substrate, wherein the dummy gate stack structure contains carbon-based materials; forming source/drain region in the substrate on both sides of the dummy gate stack structure; performing etching to remove the dummy gate stack structure until the substrate is exposed, resulting in a gate trench; and forming a gate stack structure in the gate trench. In accordance with the method for manufacturing a semiconductor device of the present invention, the dummy gate made of carbon-based materials is used to substitute the dummy gate made of silicon-based materials, then no oxide liner and/or etch blocking layer needs be added while the dummy gate is removed by etching in the gate last process, thus the reliability of device is ensured while the process is simplified and the cost is reduced.

Abstract: The present application discloses a method for manufacturing a semiconductor device, comprising: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; filling successively a gate insulation layer and a metal layer in the T-shape gate trench, wherein the metal layer forms the T-shape metal gate structure. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.

Abstract: The present invention discloses a semiconductor device, comprising a substrate, a gate stack structure on the substrate, a gate spacer structure at both sides of the gate stack structure, source/drain regions in the substrate and at opposite sides of the gate stack structure and the gate spacer structure, characterized in that the gate spacer structure comprises at least one gate spacer void filled with air. In accordance with the semiconductor device and the method for manufacturing the same of the present invention, carbon-based materials are used to form a sacrificial spacer, and at least one air void is formed after removing the sacrificial spacer, the overall dielectric constant of the spacer is effectively reduced. Thus, the gate parasitic capacitance is reduced and the device performance is enhanced.