Abstract: Methods and apparatuses for efficiently providing supply voltages to a load circuit are provided. The apparatus includes a first plurality of first power buses extending in a first direction and within a first range. The first range extends in a second direction. A second plurality of first power buses extends in the first direction and within the first range. The first plurality of first power buses and the second plurality of first power buses are powered at a first supply voltage. A plurality of second power buses extends in the first direction within the first range and a second range. The second range extends in the first direction. The plurality of second power buses is powered at a second supply voltage. The first plurality of first power buses, the second plurality of first power buses, and the plurality of second power buses are in a conductive layer.

Abstract: A method of and an apparatus for optimizing timing delay and power leakage in a circuit. The apparatus determines at least one path of a plurality of paths in a network of logic elements, the at least one path including a plurality of cells, each of the cells being configured to perform a logical operation. In addition, the apparatus identifies a first cell of the plurality of cells based on a first cost factor associated with replacing the first cell with a first replacement cell that performs the same logical operation, the first cost factor being a function of a power leakage difference and a timing delay difference associated with the first cell and the first replacement cell. Furthermore, the apparatus replaces the first cell with the first replacement cell in the at least one path.

Abstract: A method of reducing the number of hold violations in an integrated circuit comprises: determining a segment, wherein the segment is a connection between a plurality of points; associating at least one path with each segment, wherein the path is a connection of points including a starting point and an endpoint; determining a weight for at least one said segment, wherein the weight is determined by a number of paths associated with the at least one said segment; ranking the segments in a matrix based upon the determined weight associated with at least one of the segments; and inserting a buffer at least one of the segments based upon said ranking.

Abstract: A method is disclosed for programming an ID register of a microchip. The method comprises the step, prior to packaging, of attaching at least one additional ID pin to the die of the microchip. The at least one pin being so attached that, when the microchip is packaged, the at least one pin is sealed within the package. At least a portion of the microchip identity data is programmed by providing a plurality of unique combinations of binary data to the at least one additional pin. Each unique combination of binary data corresponds to a unique identity of the microchip. The at least one pin is coupled to a respective module of the microchip layout for providing, via the at least one pin, information associated with the particular identity of the microchip. The at least one pin is also coupled to the identification register, so as to, upon testing, include the respective combination of binary data in the ID register data of the microchip.

Abstract: A method of reducing the number of hold violations in an integrated circuit comprises: determining a segment, wherein the segment is a connection between a plurality of points; associating at least one path with each segment, wherein the path is a connection of points including a starting point and an endpoint; determining a weight for at least one said segment, wherein the weight is determined by a number of paths associated with the at least one said segment; ranking the segments in a matrix based upon the determined weight associated with at least one of the segments; and inserting a buffer at least one of the segments based upon said ranking.

Abstract: A method is disclosed for programming an ID register of a microchip. The method comprises the step, prior to packaging, of attaching at least one additional ID pin to the die of the microchip. The at least one pin being so attached that, when the microchip is packaged, the at least one pin is sealed within the package. At least a portion of the microchip identity data is programmed by providing a plurality of unique combinations of binary data to the at least one additional pin. Each unique combination of binary data corresponds to a unique identity of the microchip. The at least one pin is coupled to a respective module of the microchip layout for providing, via the at least one pin, information associated with the particular identity of the microchip. The at least one pin is also coupled to the identification register, so as to, upon testing, include the respective combination of binary data in the ID register data of the microchip.