Patents by Inventor Kelin ZHANG

Kelin ZHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240132407
    Abstract: The present invention relates to a ceramic slate with a colored jade effect and a preparation method comprising: pressing and forming raw materials containing a ceramic base material and colored glass fragments to obtain a ceramic green body; drying and firing the ceramic green body to give a ceramic slate with colored jade effect particles dispersed on the surface of the green body; wherein, the colored glass fragments account for 3 wt % to 5 wt % of the ceramic base material. Since colored glass waste instead of frits and pigments is used to prepare the ceramic slate with the colored jade effect, the ceramic slate does not have the phenomenon of pigment dispersion after high-temperature firing, and the surface of the fired ceramic slate shows a shape of micro-protrusion, so that the polished tile surface is smoother and free from pits, resulting in a better tile surface effect.
    Type: Application
    Filed: December 3, 2021
    Publication date: April 25, 2024
    Inventors: Yijun LIU, Yuandong YANG, Qiuli HUANG, Kelin ZHANG
  • Publication number: 20230227374
    Abstract: A preparation method includes the following steps: Step (1): pressing and then drying body powder to form a green brick; Step (2): applying a ground coat on the surface of the green brick; Step (3): inkjet-printing a pattern on the surface of the green brick having the ground coat, and applying an isolation glaze; Step (4): applying a fully polished glaze on the surface of the green brick having the isolation glaze; and Step (5): drying, firing, and polishing the green brick having the fully polished glaze to obtain a hard wear-resistant polished glazed ceramic tile. The phase composition of the fired fully polished glaze is as follows: 10 to 20 percent by weight of corundum, 20 to 30 percent by weight of hyalophane, 0.5 to 1.0 percent by weight of hematite, and 50 to 68 percent by weight of amorphous phase.
    Type: Application
    Filed: December 24, 2020
    Publication date: July 20, 2023
    Inventors: Yijun LIU, Laifu DENG, Yuandong YANG, Xianchao WANG, Kelin ZHANG
  • Publication number: 20230192569
    Abstract: The present application provides a high-wear-resistance far-infrared ceramic polished glazed tile and preparation method therefor. The preparation method includes application of far-infrared overglaze, ink-jet printing, application of transparent far-infrared polished glaze and application of abrasion-resistant far-infrared polished glaze in sequence on a body, firing, and polishing. By adopting the far-infrared overglaze, the transparent far-infrared polished glaze and the abrasion-resistant far-infrared polished glaze in combination, the polished glaze tile can have a far-infrared function, high transparency, and high abrasion resistance.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 22, 2023
    Inventors: Yijun LIU, Yuandong YANG, Kelin ZHANG, Xianchao WANG, Lingyan HUANG
  • Patent number: 10985771
    Abstract: A method of calibrating capacitive array of a resistor-capacitor hybrid successive approximation register analog-to-digital converter (RC-hybrid SAR ADC) that includes a high M-bit capacitor DAC and a low N-bit resistor DAC. The method includes: disposing n unit capacitors in each capacitive array of the RC-hybrid SAR ADC, wherein n=2M?1; sorting the capacitors in an ascending order according to their capacitances to form a sorted array, and selecting two capacitors Cu(n/2)*, Cu(n/2+1)* in the middle positions as a least significant bit (LSB) capacitor and a dummy capacitor, respectively; obtaining a new array by forming each capacitor through adding two capacitors which have symmetrical positions with respect to the middle position(s) in the sorted array; and sorting the new array in an ascending order, and selecting the capacitor in the middle position as a higher bit capacitor. The method improves the static and dynamic performance of the SAR ADC.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: April 20, 2021
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Hua Fan, Chen Wang, Peng Lei, Dainan Zhang, Quanyuan Feng, Lang Feng, Xiaopeng Diao, Dagang Li, Kelin Zhang, Daqian Hu, Yuanjun Cen
  • Publication number: 20210058091
    Abstract: A method of calibrating capacitive array of a resistor-capacitor hybrid successive approximation register analog-to-digital converter (RC-hybrid SAR ADC) that includes a high M-bit capacitor DAC and a low N-bit resistor DAC. The method includes: disposing n unit capacitors in each capacitive array of the RC-hybrid SAR ADC, wherein n=2M?1; sorting the capacitors in an ascending order according to their capacitances to form a sorted array, and selecting two capacitors Cu(n/2)*, Cu(n/2+1)* in the middle positions as a least significant bit (LSB) capacitor and a dummy capacitor, respectively; 4) obtaining a new array by forming each capacitor through adding two capacitors which have symmetrical positions with respect to the middle position(s) in the sorted array; and sorting the new array in an ascending order, and selecting the capacitor in the middle position as a higher bit capacitor. The method improves the static and dynamic performance of the SAR.
    Type: Application
    Filed: December 4, 2019
    Publication date: February 25, 2021
    Inventors: Hua FAN, Chen WANG, Peng LEI, Dainan ZHANG, Quanyuan FENG, Lang FENG, Xiaopeng DIAO, Dagang LI, Kelin ZHANG, Daqian HU, Yuanjun CEN