Abstract: An apparatus and method for efficiently migrating the execution of threads between multiple parallel lanes of execution. In various implementations, a computing system includes multiple vector processing circuits of a compute circuit that executes multiple lanes of multiple waves. Each lane includes a key indicating a path of execution. When a lane of the multiple lanes of execution executes a stream wave coalescing (SWC) reorder instruction, a control circuit compares keys of waves that have previously executed the SWC reorder instruction. When the number of lanes with a matching key exceeds a threshold and after identifying at least this number of lanes to swap, the control circuit swaps continuation state information (live active state information) between lanes of an emitting wave that do not have a matching key and lanes of contributing waves that do have a matching key. The resulting (reordered) emitting wave executes more efficiently, which increases performance.

Abstract: A Streaming Wave Coalescer (SWC) circuit stores a first set of state values associated with a first subset of threads of a first wave in a bin based on each of the first subset of threads including a first set of instructions to be executed. A second set of state values associated with a second subset of threads of a second wave is stored in the bin based on each of the second subset of threads including the first set of instructions to be executed and based on the first wave and the second wave both being associated with a hard key. A third wave is formed from the threads of the first subset and the second subset and is emitted for execution. As a result of reorganizing the threads and reconstituting a different wave, thread divergence of waves sent for execution is reduced.

Abstract: An apparatus and method for efficiently managing voltage droop among replicated compute circuits of an integrated circuit. In various implementations, an integrated circuit includes multiple, replicated compute circuits, each with the circuitry of multiple lanes of execution. Control circuitry of the integrated circuit identifies, early in execution pipelines, groups of instructions to be executed by a corresponding compute circuit, and generates a total power consumption estimate for the groups. The control circuitry maintains N previous total power consumption estimates, and stores the N power consumption estimates in staging circuitry referred to as an “instruction history pipeline.” If any differences between total power consumption estimates of different stages of the instruction history pipeline exceeds a corresponding threshold, then the control circuitry reduces, late in the execution pipeline, the rate of instruction execution of computation lanes of a corresponding compute circuit.

Abstract: A block of image data having a plurality of image element values each having a plurality of data values relating to a respective plurality of channels is compressed, wherein the channels comprise a reference channel and non-reference channels.

Abstract: Image element values are determined from compressed data representing a block of image data comprising data values relating to a respective plurality of channels including a reference channel and a plurality of non-reference channels by performing decompression. Compressed channel data is read from the compressed data and used to determine an initial data value relating to a channel for each of the image element values being decompressed.

Abstract: Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.

Abstract: Data signal items output by a radix 4n2m fast Fourier transform (“FFT”) operation may not be in the order desired for further use of those data items (e.g., they may be output in a non-natural order rather than in a desired natural order). Memory circuitry (e.g., dual-port memory circuitry) may be used in conjunction with circuitry for addressing the memory circuitry with address signals that are reordered in a particular way for each successive set of N data items. This allows use of memory circuitry with fewer data item storage locations than would otherwise be required to reorder the data items from non-natural to natural order. In particular, the memory circuitry only needs to be able to store N data items at any one time, which is more efficient memory utilization than would otherwise be possible.

Abstract: Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.

Abstract: Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.

Abstract: Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.

Abstract: Interleaving in which functions relating final and original positions are implemented with low complexity using inequalities based on the functions.

Abstract: In the provided architecture, one or more multi-threaded processors may be combined with hardware blocks having increased functionality. Each hardware block may be able to transfer a data packet to a particular hardware block based on the packet being processing. One or more hardware block may also be able to divide packets into subpackets for separate processing, and other hardware blocks may be able to rejoin the subpackets. Hardware blocks may also be able to transfer packet information between other hardware blocks during the processing sequence.

Abstract: Incoming data streams are processed at relatively high speed for decoding, content inspection and classification. A multitude of processing channels process multiple data streams concurrently so as to allows networking based host systems to provide the data streams—as the packets carrying these data streams are received from the network—without requiring the data streams to be buffered. Moreover, host systems processing stored content, such as email messages and computer files, can process more than one stream at once and thereby make better utilization of the host system's CPU. Processing bottlenecks are alleviated by offloading the tasks of data extraction, inspection and classification from the host CPU. A content processing system which so processes the incoming data streams, is readily extensible to accommodate and perform additional data processing algorithms. The content processing system is configurable to enable additional data processing algorithms to be performed in parallel or in series.