Abstract: A data detector includes a branch metric calculator operable to calculate branch metrics for transitions between states in a trellis for the data detector, and a pruning circuit operable to prune prohibited states from the trellis. The states in the trellis comprise basic states and extended states, where the extended states have a greater number of bits than the basic states.

Abstract: A data detector includes a branch metric calculator operable to calculate branch metrics for transitions between states in a trellis for the data detector, and a pruning circuit operable to prune prohibited states from the trellis. The states in the trellis comprise basic states and extended states, where the extended states have a greater number of bits than the basic states.

Abstract: Methods and apparatus are provided for high-speed, low-power, high-performance channel detection. A soft-output detector is provided for processing a received signal, comprising: a forward detector for calculating forward state metrics; a backward detector for calculating backward state metrics; and a current branch detector for calculating a current branch metric, wherein at least two of the forward detector, the backward detector and the current branch detector employ trellis structures with a different number of states. A method is provided for processing a received signal using a soft-output detector, comprising: calculating forward state metrics using a forward detector; calculating backward state metrics using a backward detector; and calculating a current branch metric using a current branch detector, wherein at least two of the forward detector, the backward detector and the current branch detector employ trellis structures with a different number of states.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data processing systems with symbol selective scaling interacting with parity forcing.

Abstract: Methods and apparatus are provided for high-speed, low-power, high-performance channel detection. A soft output channel detector is provided that operates at a rate of 1/N and detects N bits per 1/N-rate clock cycle. The channel detector comprises a plurality, D, of MAP detectors operating in parallel, wherein each of the MAP detectors generates N/D log-likelihood ratio values per 1/N-rate clock cycle and wherein at least one of the plurality of MAP detectors constrains each of the bits. The log-likelihood ratio values can be merged to form an output sequence. A single MAP detector is also provided that comprises a forward detector for calculating forward state metrics; a backward detector for calculating backward state metrics; and a current branch detector for calculating a current branch metric, wherein at least two of the forward detector, the backward detector and the current branch detector employ different trellis structures.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data processing systems with symbol selective scaling interacting with parity forcing.

Abstract: Methods and apparatus are provided for high-speed, low-power, high-performance channel detection. A soft output channel detector is provided that operates at a rate of 1/N and detects N bits per 1/N-rate clock cycle. The channel detector comprises a plurality, D, of MAP detectors operating in parallel, wherein each of the MAP detectors generates N/D log-likelihood ratio values per 1/N-rate clock cycle and wherein at least one of the plurality of MAP detectors constrains each of the bits. The log-likelihood ratio values can be merged to form an output sequence. A single MAP detector is also provided that comprises a forward detector for calculating forward state metrics; a backward detector for calculating backward state metrics; and a current branch detector for calculating a current branch metric, wherein at least two of the forward detector, the backward detector and the current branch detector employ different trellis structures.

Abstract: A methodology for designing an implementing high rate RLL codes is optimized for application to 10-bit ECC symbols, and provides rate 20/21, rate 50/51, rate 90/91 and other modulation code rates for use in magnetic recording channels. A relatively small subcode encoding—one easy to implement—is applied to a portion of the input stream, and the resulting base codeword is partitioned into nibbles that, in turn, are interleaved among the unencoded ECC symbols. Code constraints on the subcode word nibbles depend upon the values of adjacent unencoded symbols. The resulting codes provide excellent density and error propagation performance.

Abstract: A methodology for designing an implementing high rate RLL codes is optimized for application to 10-bit ECC symbols, and provides rate 20/21, rate 50/51, rate 90/91 and other modulation code rates for use in magnetic recording channels. A relatively small subcode encoding—one easy to implement—is applied to a portion of the input stream, and the resulting base codeword is partitioned into nibbles that, in turn, are interleaved among the unencoded ECC symbols. Code constraints on the subcode word nibbles depend upon the values of adjacent unencoded symbols. The resulting codes provide excellent density and error propagation performance.

Abstract: A discrete-time filtering method for identifying defects in a magnetic medium, comprising the steps of: reading data signals from at least a portion of the medium; sampling the data signals to generate discrete time sample data; processing the sample data in a discrete time filter to detect deviation of the signal corresponding to media defects; and comparing the deviation of the signal to one or more threshold values to identify corresponding defect types on the recording medium. The filter can be configured to have an impulse response substantially matched to deviation of the signal corresponding to media defects.

Abstract: A new class of fixed partial response targets are disclosed for use in a PRML magnetic medium read channel. The preferred embodiment exhibits an equalization response characterized by the polynomial 7+4*D−4*D2−5*D3−2*D4, where D represents the unit delay operator. This read channel target provides improved matching to the inherent magnetic channel over the known canonical class of targets (1−D)(1+D){circumflex over ( )}N, and thereby reduces equalization losses. The improved spectral matching reduces amplification of noise in the channel, thereby reducing bit-error-rates. The new class of targets also exhibits a spectral null at DC, reducing problems for offset cancellation circuitry and making the disk drive less sensitive to thermal asperities. It also exhibits a spectral depression rather than a spectral null at the Nyquist frequency, making quasi-catastrophic error sequences virtually impossible.

Abstract: A data channel, such as a magnetic recording/playback channel implements a time-varying maximum-transition-run code such that the code allows three consecutive transitions while it removes a dominant plus-minus-plus error-event and does not permit of four or more consecutive transitions.

Abstract: An EPR4 detector comprises a PR4 Viterbi detector and an EPR4 post-processor for improving estimated output sequence at an output of the PR4 Viterbi. The PR4 Viterbi detector produces digital estimates of coded digital information values into the channel in accordance with a path through a PR4 trellis and produces other path information relating to other paths through the PR4 trellis.

Abstract: A reliability unit is provided for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis.