Patents by Inventor Kelly K. Taylor
Kelly K. Taylor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9224478Abstract: A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells.Type: GrantFiled: March 6, 2013Date of Patent: December 29, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Richard K. Eguchi, Jon S. Choy, Chen He, Kelly K. Taylor
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Publication number: 20150067314Abstract: A microcontroller that includes a secure firmware flash controller is provided. The secure firmware flash controller utilizes a hardware assisted boot sequence that performs a firmware code validation. If the firmware code fails validation for any reason, the firmware flash controller locks out access to the firmware RAM and firmware flash controller, and passes control back to the microcontroller for further measures that are protected by security protocols on the microcontroller.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Inventors: Timothy J. Strauss, Thomas Jew, Kelly K. Taylor
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Publication number: 20140254285Abstract: A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells.Type: ApplicationFiled: March 6, 2013Publication date: September 11, 2014Inventors: Richard K. Eguchi, Jon S. Choy, Chen He, Kelly K. Taylor
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Patent number: 8719646Abstract: A new, robust non-volatile memory (NVM) reset sequence is provided in accordance with at least one embodiment, which, after reading a Test NVM portion and overwriting NVM configuration registers' default values with the values read from the Test NVM portion, does a read integrity check. If the read integrity check passes, a reset process will conclude. Otherwise, if the read integrity check fails, the reset process will re-try reading the Test NVM and overwriting the NVM configuration registers' default values. If the read integrity check still fails after a maximum number of re-tries, a fail flag will be set, and the predetermined “safe” default values will be reloaded to the NVM configuration registers, thereby assuring that the NVM device is operational.Type: GrantFiled: April 30, 2012Date of Patent: May 6, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Chen He, Kelly K. Taylor
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Publication number: 20130290797Abstract: A new, robust non-volatile memory (NVM) reset sequence is provided in accordance with at least one embodiment, which, after reading a Test NVM portion and overwriting NVM configuration registers' default values with the values read from the Test NVM portion, does a read integrity check. If the read integrity check passes, a reset process will conclude. Otherwise, if the read integrity check fails, the reset process will re-try reading the Test NVM and overwriting the NVM configuration registers' default values. If the read integrity check still fails after a maximum number of re-tries, a fail flag will be set, and the predetermined “safe” default values will be reloaded to the NVM configuration registers, thereby assuring that the NVM device is operational.Type: ApplicationFiled: April 30, 2012Publication date: October 31, 2013Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Chen He, Kelly K. Taylor
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Patent number: 8261011Abstract: A portion of a programmable memory device is configured as a one-time programmable (OTP) memory, where in response to a write access to the memory device, a memory controller determines whether the write access is associated with a memory location designated as an OTP memory location. If so, the memory controller performs a read of the memory location, and allows the write access only if each memory cell of the memory location is in an un-programmed state. Thus, only a single write access to an OTP memory location is permitted, and subsequent write attempts are disallowed. Further, to enhance detection of programmed cells, the read of the OTP memory location is performed with a lower read voltage than a read voltage associated with a write access to a non-OTP memory location, thereby improving detection of programmed memory cells in the OTP memory location.Type: GrantFiled: October 29, 2009Date of Patent: September 4, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Timothy J. Strauss, Kelly K. Taylor
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Patent number: 7958173Abstract: A circuit and method provides an estimate of a population count (popcount) of a plurality of input bit values. In one form the input bit values represent respective nodes of an integrated circuit. An approximation circuit uses an approximation input stage which receives a plurality of data inputs and has a plurality of logic circuits. Each logic circuit provides a single bit output. The approximation circuit provides monotonic accuracy. A reduction tree receives the single bit outputs of the plurality of logic circuits and provides an approximate count of how many of the plurality of data inputs are asserted. Size and speed are improved by providing the estimate as opposed to an exact value.Type: GrantFiled: July 13, 2007Date of Patent: June 7, 2011Assignee: Freescale Semiconductor, Inc.Inventors: William C. Moyer, Kelly K. Taylor
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Publication number: 20110107010Abstract: A portion of a programmable memory device is configured as a one-time programmable (OTP) memory, where in response to a write access to the memory device, a memory controller determines whether the write access is associated with a memory location designated as an OTP memory location. If so, the memory controller performs a read of the memory location, and allows the write access only if each memory cell of the memory location is in an un-programmed state. Thus, only a single write access to an OTP memory location is permitted, and subsequent write attempts are disallowed. Further, to enhance detection of programmed cells, the read of the OTP memory location is performed with a lower read voltage than a read voltage associated with a write access to a non-OTP memory location, thereby improving detection of programmed memory cells in the OTP memory location.Type: ApplicationFiled: October 29, 2009Publication date: May 5, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Timothy J. Strauss, Kelly K. Taylor
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Patent number: 7931190Abstract: A circuit includes a plurality of selection circuits. Each of the plurality of selection circuits has a first input, a second input, a control input, and an output. Each of the first inputs receives one of a plurality of correlated signals. Each of the second inputs receives one of a plurality of uncorrelated signals. Each of the control inputs receives a correlation mode control signal, and each of the outputs provides the one of the plurality of correlated signals or the one of the plurality of uncorrelated signals based on the correlation mode control signal. The circuit further includes a population count circuit having a plurality of data inputs coupled to receive the outputs of the plurality of selection circuits. The population count circuit provides a population count for the plurality of data inputs. The population count may be an approximate count or an accurate count.Type: GrantFiled: July 13, 2007Date of Patent: April 26, 2011Assignee: Freescale Semiconductor, Inc.Inventors: William C. Moyer, Kelly K. Taylor
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Publication number: 20090016480Abstract: A circuit includes a plurality of selection circuits. Each of the plurality of selection circuits has a first input, a second input, a control input, and an output. Each of the first inputs receives one of a plurality of correlated signals. Each of the second inputs receives one of a plurality of uncorrelated signals. Each of the control inputs receives a correlation mode control signal, and each of the outputs provides the one of the plurality of correlated signals or the one of the plurality of uncorrelated signals based on the correlation mode control signal. The circuit further includes a population count circuit having a plurality of data inputs coupled to receive the outputs of the plurality of selection circuits. The population count circuit provides a population count for the plurality of data inputs. The population count may be an approximate count or an accurate count.Type: ApplicationFiled: July 13, 2007Publication date: January 15, 2009Inventors: William C. Moyer, Kelly K. Taylor
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Publication number: 20090019100Abstract: A circuit and method provides an estimate of a population count (popcount) of a plurality of input bit values. In one form the input bit values represent respective nodes of an integrated circuit. An approximation circuit uses an approximation input stage which receives a plurality of data inputs and has a plurality of logic circuits. Each logic circuit provides a single bit output. The approximation circuit provides monotonic accuracy. A reduction tree receives the single bit outputs of the plurality of logic circuits and provides an approximate count of how many of the plurality of data inputs are asserted. Size and speed are improved by providing the estimate as opposed to an exact value.Type: ApplicationFiled: July 13, 2007Publication date: January 15, 2009Inventors: William C. Moyer, Kelly K. Taylor