Abstract: A method and circuits for implementing a hacking detection and block function at indeterminate times, and a design structure on which the subject circuit resides are provided. A circuit includes an antenna wrapped around a dynamic bus inside circuitry to be protected. The antenna together with the dynamic bus node is designed so an average bus access activates a field effect transistor (FET) that is connected to a capacitor. The FET drains the capacitor in a specified number of activations by the antenna. The capacitor has a leakage path to a voltage supply rail VDD that charges the capacitor back high after a time, such as ten to one hundred cycles, of the dynamic bus being quiet. The capacitor provides a hacking detect signal for temporarily blocking operation of the circuitry to be protected responsive to determining that the dynamic bus is more active than functionally expected.

Abstract: A semiconductor chip has a FinFET structure with three independently controllable FETs on a single fin. The three FETs are connected in parallel so that current will flow between a common source and a common drain if one or more of the three independently controllable FETs is turned on. The three independently controllable FETs may be used in logic gates.

Abstract: A method and an eFuse circuit for implementing with enhanced eFuse blow operation without requiring a separate high current and high voltage supply to blow the eFuse, and a design structure on which the subject circuit resides are provided. The eFuse circuit includes an eFuse connected to a field effect transistor (FET) operatively controlled during a sense mode and a blow mode for sensing and blowing the eFuse. The eFuse circuit is placed over an independently voltage controlled silicon region. During a sense mode, the independently voltage controlled silicon region is grounded providing an increased threshold voltage of the FET. During a blow mode, the independently voltage controlled silicon region is charged to a voltage supply potential. The threshold voltage of the FET is reduced by the charged independently voltage controlled silicon region for providing enhanced FET blow function.

Abstract: A semiconductor chip has an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. A bottom, or floor, of the independently voltage controlled silicon region is a deep implant of opposite doping to a doping of a substrate of the independently voltage controlled silicon region. A top, or ceiling, of the independently voltage controlled silicon region is a buried oxide implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation. Voltage of the independently voltage controlled silicon region is applied through a contact structure formed through the buried oxide.

Abstract: A semiconductor chip has an embedded dynamic random access memory (eDRAM) in an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM deep trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. Retention time and performance of the eDRAM is controlled by applying a voltage to the independently voltage controlled silicon region.

Abstract: A method and circuits for implementing a temporary disable function at indeterminate times of circuitry to be protected in a semiconductor chip, such as in an integrated circuit or a system on a chip (SOC) by modulating threshold voltage shifts of a timing sensitive circuit, and a design structure on which the subject circuit resides are provided. The timing sensitive circuit is designed to be sensitive to threshold-voltage shifts and is placed over an independently voltage controlled silicon region. Upon startup, the independently voltage controlled silicon region is grounded, and then is left floating. Each time a hack attempt or predefined functional oddity is detected, charge is applied onto the independently voltage controlled silicon region. After a defined charge has accumulated, the device threshold voltages in the timing sensitive circuit above the independently voltage controlled silicon region are modulated causing the timing-sensitive circuit to fail.

Abstract: A method and circuits for implementing a hacking detection and block function at indeterminate times, and a design structure on which the subject circuit resides are provided. A circuit includes an antenna wrapped around a dynamic bus inside circuitry to be protected. The antenna together with the dynamic bus node is designed so an average bus access activates a field effect transistor (FET) that is connected to a capacitor. The FET drains the capacitor in a specified number of activations by the antenna. The capacitor has a leakage path to a voltage supply rail VDD that charges the capacitor back high after a time, such as ten to one hundred cycles, of the dynamic bus being quiet. The capacitor provides a hacking detect signal for temporarily blocking operation of the circuitry to be protected responsive to determining that the dynamic bus is more active than functionally expected.

Abstract: A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor.

Abstract: A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node.

Abstract: A semiconductor chip has self aligned (where a gate electrode and associated spacers define the source/drain implant with respect to the gate electrode) Field Effect Transistors (FETs) in a back end of the line (BEOL) portion of the semiconductor chip. The FETs are used to make buffer circuits in the BEOL to improve delay and signal integrity of long signal paths on the semiconductor chip.

Abstract: A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions.

Abstract: Vertically stacked Field Effect Transistors (FETs) are created on a vertical structure formed on a semiconductor substrate where a first FET and a second FET are controllable independently. A bipolar junction transistor is connected between and in series with the first FET and the second FET, the bipolar junction transistor may be controllable independently of the first and second FET.

Abstract: A vertical structure is formed upon a semiconductor substrate. The vertical structure comprises four dielectric layers parallel to a top surface of the semiconductor substrate and three conducting layers, one conducting layer between each vertically adjacent dielectric layer. A first FET (field effect transistor) and a third FET are arranged parallel to the top surface of the semiconductor and a second FET is arranged orthogonal to the top surface of the semiconductor. All three FETs are independently controllable. The first conducting layer is a gate electrode of the first FET; the second conducting layer is a gate electrode of the second FET, and the third conducting layer is the gate electrode of the third FET.

Abstract: A method for making multilayer thin films is disclosed. The method of comprises orienting a thick multilayer film in the machine direction at a drawdown ratio effective to produce a multilayer thin film. The thick multilayer film has a thickness within the range of 1 mil to 5 mils and comprises at least one layer of a linear low density polyethylene (LLDPE) and at least one layer of a high density polyethylene (HDPE) or a medium density polyethylene (MDPE).

Abstract: A method and circuit for implementing an embedded dynamic random access memory (eDRAM), and a design structure on which the subject circuit resides are provided. The embedded dynamic random access memory (eDRAM) circuit includes a stacked field effect transistor (FET) and capacitor. The capacitor is fabricated directly on top of the FET to build the eDRAM.

Abstract: A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions.

Abstract: A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions.

Abstract: A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions.

Abstract: Ethylene copolymers valuable for films, coatings, sheets, and molded articles are disclosed. Some of the copolymers have a long-chain-branching index from 0.25 to 0.60 and a gpcBR index from 0.1 to 0.7. Others have a primary DSC melting point that is less than its secondary DSC melting point. Also disclosed is LLDPE in which the weight percentage of the low-temperature elution fraction exceeds that of the high-temperature fraction, and wherein the Mw of the low-temperature fraction exceeds that of the high-temperature fraction. The ethylene copolymers process easily, even at low melt indices, and films from the copolymers have high stiffness, good impact resistance, and high heat-seal strength over a wide temperature range.

Abstract: The present invention describes a system for modifying polymer composite surfaces to achieve 100% adhesion to paints, coatings, adhesives, or inks. The adhesion modification technology overcomes the deficiencies of energy-based treatment technologies common with wood-like polymer composites produced using various types of fillers and reinforcements, and specifically those containing cellulose and lignin.