Patents by Inventor Kelly Larson

Kelly Larson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for evaluation of scalable symmetric multiple processor cache coherency protocols and algorithms
    Patent number: 6883071
    Abstract: A system and method of evaluating cache coherency protocols and algorithms in scalable symmetric multiple processor computer systems. The system includes scalable 32-byte or larger cache lines wherein one specific byte in the cache line is assigned for write and read transactions for each specific 32-bit processor. The method includes steps to ensure each 32-bit processor writes and reads to and from the specific byte in the cache line assigned to that 32-bit processor.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: April 19, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert D. Bushey, Kelly Larson
  • Method for evaluation of scalable symmetric multiple processor cache coherency protocols and algorithms
    Publication number: 20040210719
    Abstract: A system and method of evaluating cache coherency protocols and algorithms in scalable symmetric multiple processor computer systems. The system includes scalable 32-byte or larger cache lines wherein one specific byte in the cache line is assigned for write and read transactions for each specific 32-bit processor. The method includes steps to ensure each 32-bit processor writes and reads to and from the specific byte in the cache line assigned to that 32-bit processor.
    Type: Application
    Filed: May 10, 2004
    Publication date: October 21, 2004
    Inventors: Robert D. Bushey, Kelly Larson
  • Method for evaluation of scalable symmetric multiple processor cache coherency protocols and algorithms
    Patent number: 6745299
    Abstract: A system and method of evaluating cache coherency protocols and algorithms in scalable symmetric multiple processor computer systems. The system includes scalable 32-byte or larger cache lines wherein one specific byte in the cache line is assigned for write and read transactions for each specific 32-bit processor. The method includes steps to ensure each 32-bit processor writes and reads to and from the specific byte in the cache line assigned to that 32-bit processor.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: June 1, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert D. Bushey, Kelly Larson
  • Method for evaluation of scalable symmetric multiple processor cache coherency protocols and algorithms
    Publication number: 20030097527
    Abstract: A system and method of evaluating cache coherency protocols and algorithms in scalable symmetric multiple processor computer systems. The system includes scalable 32-byte or larger cache lines wherein one specific byte in the cache line is assigned for write and read transactions for each specific 32-bit processor. The method includes steps to ensure each 32-bit processor writes and reads to and from the specific byte in the cache line assigned to that 32-bit processor.
    Type: Application
    Filed: November 19, 2001
    Publication date: May 22, 2003
    Inventors: Robert D. Bushey, Kelly Larson