Patents by Inventor Kelvin Aik Boo TAN

Kelvin Aik Boo TAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240203842
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a circuit substrate comprising a first substrate surface, a second substrate surface arranged opposite to the first substrate surface, and a substrate edge that extends from the first substrate surface to the second substrate surface; a series of holes arranged along the substrate edge of the circuit substrate, wherein each hole of the series of holes extends at least partially from the first substrate surface toward the second substrate surface; at least one die arranged on the first substrate surface; and a package casing disposed over the first substrate surface, wherein the package casing encapsulates the at least one die and the first substrate surface, and wherein the package casing fills each hole of the series of holes.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 20, 2024
    Inventors: Seng Kim YE, Kelvin Aik Boo TAN, Hong Wan NG, Chin Hui CHONG, Ling PAN, See Hiong LEOW
  • Publication number: 20240194630
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate including multiple first electrical contacts and multiple bondable pillars. In some implementations, each bondable pillar, of the multiple bondable pillars, may be coupled to a corresponding first electrical contact, of the multiple first electrical contacts. The semiconductor device assembly may further include one or more dies coupled to the substrate and including multiple second electrical contacts. In some implementations, the semiconductor device assembly may include multiple wire bonds, with each wire bond, of the multiple wire bonds, bonding a second electrical contact, of the multiple second electrical contacts, to a bondable pillar, of the multiple bondable pillars.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 13, 2024
    Inventors: See Hiong LEOW, Hong Wan NG, Seng Kim YE, Kelvin Aik Boo TAN, Ling PAN
  • Publication number: 20240194547
    Abstract: A variety of applications can include systems having packaged electronic devices. One or more of the packaged electronic devices can include a package substrate, having a first section and a second section with the second section elevated with respect to the first section, to support dies in the two sections. The first section can have a first top surface and a bottom surface with one or more layers of material between the first top surface and the bottom surface. The second section can include a second top surface and the bottom surface of the first section with the one or more layers of material of the first section extending horizontally from the first section. The second section can have one or more additional layers of material between the second top surface and the one or more layers of material of the first section extending horizontally from the first section.
    Type: Application
    Filed: November 22, 2023
    Publication date: June 13, 2024
    Inventors: Ling Pan, Seng Kim Ye, Hong Wan Ng, Kelvin Aik Boo Tan, See Hiong Leow
  • Publication number: 20240162206
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate and multiple first electrical contacts disposed on the substrate. The semiconductor device assembly may include a load switch coupled to the substrate and including a first outer surface facing the substrate and an opposing second outer surface facing away from the substrate. The load switch may include multiple second electrical contacts disposed on the second outer surface. The semiconductor device assembly may include multiple wire bonds electrically coupling the load switch to the substrate, wherein each wire bond electrically couples a corresponding first electrical contact, of the multiple first electrical contacts, to a corresponding second electrical contact, of the multiple second electrical contacts.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 16, 2024
    Inventors: Seng Kim YE, Hong Wan NG, Kelvin Aik Boo TAN, See Hiong LEOW, Ling PAN
  • Publication number: 20240162207
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor package includes a substrate, a semiconductor die disposed on the substrate, and a passive electronic component disposed on the semiconductor die.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 16, 2024
    Inventors: Kelvin Aik Boo TAN, Hong Wan NG, See Hiong LEOW, Seng Kim YE, Ling PAN
  • Publication number: 20240128182
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a base layer, a dielectric interposer coupled to the base layer and including a first outer surface facing the base layer and an opposing second outer surface facing away from the base layer and spaced apart from the first outer surface in a direction, a first electrical-connection cut-in in the second outer surface that extends, in the direction, toward the first outer surface, and one or more first electrical connections disposed within the first electrical-connection cut-in such that at least a portion of the one or more first electrical connections does not extend, in the direction, beyond the second outer surface.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 18, 2024
    Inventors: Chin Hui CHONG, Seng Kim YE, Hong Wan NG, Kelvin Aik Boo TAN
  • Publication number: 20240071886
    Abstract: Methods, systems, and devices for multi-chip package with enhanced conductive layer adhesion are described. In some examples, a conductive layer (e.g., a conductive trace) may be formed above a substrate. An integrated circuit may be bonded to the conductive layer and an encapsulant may be deposited at least between the integrated circuit and the conductive layer. In some examples, one or more surface features or one or more recesses may be formed on or within the conductive layer and the encapsulant may adhere to the surface features or recesses.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Hong Wan Ng, Seng Kim Ye, Kelvin Aik Boo Tan, Chin Hui Chong
  • Publication number: 20240063201
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate, a flip chip die electrically coupled to the substrate via a plurality of electrical connections, and a non-conductive film disposed between the flip chip die and the substrate. The non-conductive film may surround the plurality of electrical connections and mechanically couple the flip chip die to the substrate.
    Type: Application
    Filed: August 17, 2022
    Publication date: February 22, 2024
    Inventors: See Hiong LEOW, Hong Wan NG, Seng Kim YE, Kelvin Aik Boo TAN, Ling PAN
  • Publication number: 20240063168
    Abstract: Methods, systems, and devices for wire bonding for stacked memory dies are described. A memory system may include a stack of memory dies. As the stack grows to include more and more memory dies, the length of the wires coupling the memory dies with the control circuit may increase. Bonding multiple wires using an adhesive may increase a gap between neighboring wires coupled with the same memory die or different memory dies. For example, bonding one wire to a neighboring wire may pull one or both of the bonded wires away from their original placement, increasing a gap between the bonded wires and one or more neighboring wires. Bonding the wires coupled with a lower memory die may increase a gap such that sagging wires coupled with an upper memory die may be positioned in the gap to avoid shorting with the lower wires.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 22, 2024
    Inventors: See Hiong Leow, Hong Wan NG, Seng Kim Ye, Kelvin Aik Boo Tan, Ling Pan
  • Publication number: 20240063135
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a first semiconductor die, a second semiconductor die in a stacked arrangement with the first semiconductor die, and a flexible interposer disposed between the first semiconductor die and the second semiconductor die. The flexible interposer may include a first flexible layer, a second flexible layer, and a conductive trace disposed between the first flexible layer and the second flexible layer. A spacer portion of the flexible interposer may space the first semiconductor die from the second semiconductor die. A connecting portion of the flexible interposer may extend from the spacer portion beyond edges of the first semiconductor die and the second semiconductor die.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 22, 2024
    Inventors: Hong Wan NG, Seng Kim YE, Kelvin Aik Boo TAN, See Hiong LEOW, Ling PAN
  • Publication number: 20240021545
    Abstract: Implementations described herein relate to various apparatuses and integrated assemblies. In some implementations, an apparatus may include a substrate having a first surface and a second surface that is on an opposite side of the substrate with respect to the first surface. The apparatus may include an integrated circuit disposed on the substrate. The apparatus may include a decoupling capacitor configured to stabilize an input voltage supplied to the integrated circuit, wherein all electrodes of the decoupling capacitor are entirely within a region between the first surface and the second surface.
    Type: Application
    Filed: July 14, 2022
    Publication date: January 18, 2024
    Inventors: Wen Wei LUM, Kelvin Aik Boo TAN, Alaa N. ALI