Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate and multiple first electrical contacts disposed on the substrate. The semiconductor device assembly may include a load switch coupled to the substrate and including a first outer surface facing the substrate and an opposing second outer surface facing away from the substrate. The load switch may include multiple second electrical contacts disposed on the second outer surface. The semiconductor device assembly may include multiple wire bonds electrically coupling the load switch to the substrate, wherein each wire bond electrically couples a corresponding first electrical contact, of the multiple first electrical contacts, to a corresponding second electrical contact, of the multiple second electrical contacts.

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor package includes a substrate, a semiconductor die disposed on the substrate, and a passive electronic component disposed on the semiconductor die.

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a base layer, a dielectric interposer coupled to the base layer and including a first outer surface facing the base layer and an opposing second outer surface facing away from the base layer and spaced apart from the first outer surface in a direction, a first electrical-connection cut-in in the second outer surface that extends, in the direction, toward the first outer surface, and one or more first electrical connections disposed within the first electrical-connection cut-in such that at least a portion of the one or more first electrical connections does not extend, in the direction, beyond the second outer surface.

Abstract: Methods, systems, and devices for multi-chip package with enhanced conductive layer adhesion are described. In some examples, a conductive layer (e.g., a conductive trace) may be formed above a substrate. An integrated circuit may be bonded to the conductive layer and an encapsulant may be deposited at least between the integrated circuit and the conductive layer. In some examples, one or more surface features or one or more recesses may be formed on or within the conductive layer and the encapsulant may adhere to the surface features or recesses.

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate, a flip chip die electrically coupled to the substrate via a plurality of electrical connections, and a non-conductive film disposed between the flip chip die and the substrate. The non-conductive film may surround the plurality of electrical connections and mechanically couple the flip chip die to the substrate.

Abstract: Methods, systems, and devices for wire bonding for stacked memory dies are described. A memory system may include a stack of memory dies. As the stack grows to include more and more memory dies, the length of the wires coupling the memory dies with the control circuit may increase. Bonding multiple wires using an adhesive may increase a gap between neighboring wires coupled with the same memory die or different memory dies. For example, bonding one wire to a neighboring wire may pull one or both of the bonded wires away from their original placement, increasing a gap between the bonded wires and one or more neighboring wires. Bonding the wires coupled with a lower memory die may increase a gap such that sagging wires coupled with an upper memory die may be positioned in the gap to avoid shorting with the lower wires.

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a first semiconductor die, a second semiconductor die in a stacked arrangement with the first semiconductor die, and a flexible interposer disposed between the first semiconductor die and the second semiconductor die. The flexible interposer may include a first flexible layer, a second flexible layer, and a conductive trace disposed between the first flexible layer and the second flexible layer. A spacer portion of the flexible interposer may space the first semiconductor die from the second semiconductor die. A connecting portion of the flexible interposer may extend from the spacer portion beyond edges of the first semiconductor die and the second semiconductor die.

Abstract: Implementations described herein relate to various apparatuses and integrated assemblies. In some implementations, an apparatus may include a substrate having a first surface and a second surface that is on an opposite side of the substrate with respect to the first surface. The apparatus may include an integrated circuit disposed on the substrate. The apparatus may include a decoupling capacitor configured to stabilize an input voltage supplied to the integrated circuit, wherein all electrodes of the decoupling capacitor are entirely within a region between the first surface and the second surface.