Abstract: A die-to-die (D2D) interface between chiplets of a system on a chip (SoC) in which each of the chiplets are subdivided into slices. The D2D interface includes a transmission interface coupled between first and second chiplets, which includes a first transmission path for a first slice and a second transmission path for a second slice. The first chiplet includes receive circuitry which further includes a write interface and a read interface. The write interface stores data received from the first transmission path into a first FIFO using a first clock signal received via the first transmission path, and stores data received from the second transmission path into a second FIFO using a second clock signal received via the second transmission path. The read interface reads data stored in the first and second FIFOs using the first clock signal. The first and second transmission paths may be subject to different delays.

Abstract: A method includes allocating a first single-cycle instruction to a first pipeline that picks single-cycle instructions for execution in program order. The method further includes marking at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to all older single-cycle instructions allocated to the first pipeline being ready and eligible to be picked for execution. An apparatus includes a decoder to decode a first single-cycle instruction and to allocate the first single-cycle instruction to a first pipeline. The apparatus further includes a scheduler to pick single-cycle instructions for execution by the first pipeline in program order and to mark at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to determining that all older single-cycle instructions allocated to the first pipeline are ready and eligible.

Abstract: The present application provides a method and apparatus for supporting denormal numbers in a floating point multiply-add unit (FMAC). One embodiment of the FMAC is configurable to add a product of first and second operands to a third operand. This embodiment of the FMAC is configurable to determine a minimum exponent shift for a sum of the product and the third operand by subtracting a minimum normal exponent from a product exponent of the product. This embodiment of the FMAC is also configurable to cause bits representing the sum to be left shifted by the minimum exponent shift if a third exponent of the third operand is less than or equal to the product exponent and the minimum exponent shift is less than or equal to a predicted left shift for the sum.

Abstract: A method includes allocating a first single-cycle instruction to a first pipeline that picks single-cycle instructions for execution in program order. The method further includes marking at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to all older single-cycle instructions allocated to the first pipeline being ready and eligible to be picked for execution. An apparatus includes a decoder to decode a first single-cycle instruction and to allocate the first single-cycle instruction to a first pipeline. The apparatus further includes a scheduler to pick single-cycle instructions for execution by the first pipeline in program order and to mark at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to determining that all older single-cycle instructions allocated to the first pipeline are ready and eligible.

Abstract: The present application provides a method and apparatus for supporting denormal numbers in a floating point multiply-add unit (FMAC). One embodiment of the FMAC is configurable to add a product of first and second operands to a third operand. This embodiment of the FMAC is configurable to determine a minimum exponent shift for a sum of the product and the third operand by subtracting a minimum normal exponent from a product exponent of the product. This embodiment of the FMAC is also configurable to cause bits representing the sum to be left shifted by the minimum exponent shift if a third exponent of the third operand is less than or equal to the product exponent and the minimum exponent shift is less than or equal to a predicted left shift for the sum.

Abstract: A processor includes a prediction circuit and a floating point unit. The prediction circuit is configured to predict an execution latency of a floating point operation. The floating point unit is coupled to receive the floating point operation for execution, and is configured to detect a misprediction of the execution latency. In some embodiments, an exception may be taken in response to the misprediction. In other embodiments, the floating point operation may be rescheduled with the corrected execution latency.

Abstract: A multiplier includes a plurality of subunits. Each of the plurality of subunits is configured to perform a portion of a multiplication operation, and the plurality of subunits are coupled together to perform the multiplication operation. At least a first subunit of the plurality of subunits and a second subunit of the plurality of subunits are configured to perform a same portion of the multiplication operation. The first subunit and the second subunit are clocked at a first clock frequency, during use, that is less than a second clock frequency at which a remainder of the plurality of subunits are clocked during use. The first subunit and the second subunit each have inputs coupled to a third subunit of the plurality of subunits to receive multiplication operations to be operated upon by the respective first subunit and second subunit.

Abstract: A reservation station with format conversion logic enables the implementation of a superscalar computer processing system which incorporates both a floating point functional unit and non-floating point functional units. By converting operand data in a floating point reservation station from external formats to an internal floating point format, a system incorporating such a floating point reservation station enables the representation of operand data in uniform external formats outside floating point arithmetic units (e.g., in a reorder buffer, on operand and result busses, and within non-floating functional units) while also enabling the use of a specialized internal representation (internal floating point format) within floating point arithmetic units.

Abstract: A reservation station with format conversion logic enables the implementation of a superscalar computer processing system which incorporates both a floating point functional unit and non-floating point functional units. By converting operand data in a floating point reservation station from external formats to an internal floating point format, a system incorporating such a floating point reservation station enables the representation of operand data in uniform external formats outside floating point arithmetic units (e.g., in a reorder buffer, on operand and result busses, and within non-floating functional units) while also enabling the use of a specialized internal representation (internal floating point format) within floating point arithmetic units.

Abstract: A reservation station with an addressable constant store enables the provision of floating point constants to arithmetic units in a floating point unit of a superscalar processor. Floating point constant identifiers supplied with floating point instructions index into the addressable store and addressed constant are provided in an internal, extended-precision format which provides extra precision and/or range when compared with formats available external to the floating point unit. In this way, full internal, extended-precision constants can be provided for use in microcoded floating point instruction sequences. Additionally, internal extended-precision floating point constants may be rounded in accordance with a prevailing rounding mode and format to provide external format floating point constant values for use in implementing load constant instructions.

Abstract: Logic for selectively forcing arithmetic results allows a floating point unit to bypass the normal flow through arithmetic units and pipelines depending on the particular floating point operation and operand conditions. Certain forced results (e.g., forced zeros, infinities, and those corresponding to certain invalid operand conditions) may bypass arithmetic units or pipelines and rounding circuitry entirely. On the other hand, other operand dependent results (e.g., the result of X+0 and results of operations involving a NaN operand or operands) may only partially bypass the normal flow. By providing logic for selectively forcing results, arithmetic pipelines may be freed for subsequent instructions in the instruction stream. Logic for selectively forcing arithmetic results may be particularly attractive in a superscalar processor.