Patents by Inventor Kelvin L. Holub

Kelvin L. Holub has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus for performing wafer-level testing of integrated circuits where the wafer uses a segmented conductive top-layer bus structure
    Patent number: 5654588
    Abstract: Wafer level testing of a wafer (500) is accomplished by dividing the integrated circuits of the wafer into a plurality of segmented bus regions (514, 516, and 518 for example). Each bus region is formed having its own set of test conductors (520-530) wherein each set of test conductors are isolated from all other sets of test conductors on the wafer. Each test conductor has at least one contact pad (531-546) where each contact pad lies within a periphery of the integrated circuits' active areas. By forming pads over ICs and by sub-dividing the bus structure of test conductive lines, more high powered ICs can be tested in a wafer-level manner with fewer problems associated with speed, power, throughput, and routing problems.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 5, 1997
    Assignee: Motorola Inc.
    Inventors: Edward C. Dasse, Robert W. Bollish, Alfredo Figueroa, James H. Carlquist, Thomas R. Yarbrough, Charles F. Toewe, Kelvin L. Holub, Marcus R. Burton, Kenneth J. Long, Walid S. Ballouli, Shih King Cheng
  • Apparatus for performing wafer level testing of integrated circuit dice
    Patent number: 5504369
    Abstract: A semiconductor wafer (20) having integrated circuit dice (22), wafer conductors (42-47, 50-53), and wafer contact pads (38) formed thereon. The wafer conductors (42-47, 50-53) are used to transfer electrical signals to and from the integrated circuit dice (22) on semiconductor wafer (20) so that wafer level testing and burn-in can be performed on the integrated circuit dice (22). In accordance with one embodiment of the present, each wafer conductor (45, 52) is electrically coupled to the same bonding pad (78) on each integrated circuit dice (22). Each wafer conductor (42-47, 50-53) includes at least a portion of conductor (42-47) which overlies the upper surface of at least one integrated circuit dice (22).
    Type: Grant
    Filed: November 21, 1994
    Date of Patent: April 2, 1996
    Assignee: Motorola Inc.
    Inventors: Edward C. Dasse, Robert W. Bollish, Alfredo Figueroa, James H. Carlquist, Thomas R. Yarbrough, Charles F. Toewe, Kelvin L. Holub, Marcus R. Burton, Kenneth J. Long, Walid S. Ballouli
  • Method and apparatus for performing wafer level testing of integrated circuit dice
    Patent number: 5399505
    Abstract: A semiconductor wafer (20) having integrated circuit dice (22), wafer conductors (42-47, 50-53), and wafer contact pads (38) formed thereon. The wafer conductors (42-47, 50-53) are used to transfer electrical signals to and from the integrated circuit dice (22) on semiconductor wafer (20) so that wafer level testing and burn-in can be performed on the integrated circuit dice (22). In accordance with one embodiment of the present, each wafer conductor (45, 52) is electrically coupled to the same bonding pad (78) on each integrated circuit dice (22). Each wafer conductor (42-47, 50-53) includes at least a portion of conductor (42-47) which overlies the upper surface of at least one integrated circuit dice (22).
    Type: Grant
    Filed: July 23, 1993
    Date of Patent: March 21, 1995
    Assignee: Motorola, Inc.
    Inventors: Edward C. Dasse, Robert W. Bollish, Alfredo Figueroa, James H. Carlquist, Thomas R. Yarbrough, Charles F. Toewe, Kelvin L. Holub, Marcus R. Burton, Kenneth J. Long, Walid S. Ballouli, Shih K. Cheng