Patents by Inventor Kelvin Marino

Kelvin Marino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240134757
    Abstract: Systems and methods for enabling serial attached Non-Volatile (NV) memory are provided. In some embodiments, a method of operation of a computing system includes: in an NV Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a NV Controller unit (NVC), and a serial host interface, the method includes: receiving a request for data on the serial host interface and providing the requested data, from the volatile memory device, on the serial host interface. The method also includes: detecting a disruptive volatile memory event; copying the data of the volatile memory device to the NV device through the serial host interface based on the disruptive volatile memory event; and restoring the data of the volatile memory device from the NV device through the serial host interface. In this way, Dynamic Random-Access Memory (DRAM) level endurance and speed/latency can be provided while making it NV.
    Type: Application
    Filed: December 29, 2023
    Publication date: April 25, 2024
    Inventors: Torry Steed, Kelvin Marino, Jinying Shen, Itsik Yomorta
  • Publication number: 20230305922
    Abstract: Systems and methods for enabling serial attached Non-Volatile (NV) memory are provided. In some embodiments, a method of operation of a computing system including: in an NV Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a NV Controller unit (NVC), and a serial host interface, the method includes: receiving a request for data on the serial host interface and providing the requested data, from the volatile memory device with data, on the serial host interface. The method also includes: detecting a disruptive volatile memory event; copying the data of the volatile memory device to the NV device based on the disruptive volatile memory event; and restoring the data of the volatile memory device from the NV device. In this way, Dynamic Random-Access Memory (DRAM) level endurance and speed/latency can be provided while making it NV.
    Type: Application
    Filed: March 24, 2022
    Publication date: September 28, 2023
    Inventors: Robert Tower Frey, Kelvin Marino
  • Patent number: 10755757
    Abstract: A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: August 25, 2020
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Hossein Amidi, Kelvin A. Marino, Satyadev Kolli
  • Patent number: 9779016
    Abstract: An integrated circuit system, and a method of operation thereof, including: a memory unit having a volatile memory device with data and a non-volatile controller unit; a memory unit controller of the non-volatile controller unit for receiving a snoop signal for indicating an error; a non-volatile device of the memory unit for synchronously receiving data of the volatile memory device based on the snoop signal, the data autonomously copied without any intervention from outside the memory unit to prevent loss of the data; and an in-band command received by the memory unit, for autonomously restoring the data to the volatile memory device from the non-volatile device without any intervention from outside the memory unit.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: October 3, 2017
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Jinying Shen, Robert Tower Frey, Kelvin Marino
  • Patent number: 9754634
    Abstract: A method of manufacture of the memory management system includes: fabricating a dual in-line memory module carrier; mounting a volatile memory device on the dual in-line memory module carrier; mounting a non-volatile memory on the dual in-line memory module carrier on a side opposite the volatile memory device; mounting an uninterruptible power supply on the dual in-line memory module carrier for maintaining a memory module power when a system power input decays; and mounting a controller logic integrated circuit on the dual in-line memory module carrier coupled to the volatile memory device, the non-volatile memory, and the uninterruptible power supply for copying data content of the volatile memory device to the non-volatile memory when the uninterruptible power supply detects the decay of the system power input to a first cross-over level.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: September 5, 2017
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Jinying Shen, Robert Tower Frey, Kelvin Marino, Joshua Harris Brooks
  • Patent number: 8990489
    Abstract: A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: March 24, 2015
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Hossein Amidi, Kelvin A. Marino, Satyadev Kolli
  • Patent number: 8767463
    Abstract: A method of operation of a non-volatile dynamic random access memory system including: accessing a dynamic random access memory; managing a delay-locked-loop control in the dynamic random access memory; sourcing timing inputs to the dynamic random access memory by a control logic unit with the delay-locked-loop control disabled including: selecting a back-up interface through a first multiplexer and a second multiplexer, asserting an on-board termination, and accessing data in the dynamic random access memory by the control logic unit at a lower frequency; and enabling a memory control interface by the control logic unit, with the delay-locked-loop control enabled including: selecting a host interface through the first multiplexer, the second multiplexer, or a combination thereof, disabling the on-board termination, and accessing the data in the dynamic random access memory by the memory control interface at a delay-locked-loop frequency.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: July 1, 2014
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Mike H. Amidi, Kelvin Marino
  • Patent number: 8626998
    Abstract: A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: January 7, 2014
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Mike Hossein Amidi, Kelvin A. Marino, Satyadev Kolli
  • Publication number: 20130128685
    Abstract: A method of manufacture of the memory management system includes: fabricating a dual in-line memory module carrier; mounting a volatile memory device on the dual in-line memory module carrier; mounting a non-volatile memory on the dual in-line memory module carrier on a side opposite the volatile memory device; mounting an uninterruptible power supply on the dual in-line memory module carrier for maintaining a memory module power when a system power input decays; and mounting a controller logic integrated circuit on the dual in-line memory module carrier coupled to the volatile memory device, the non-volatile memory, and the uninterruptible power supply for copying data content of the volatile memory device to the non-volatile memory when the uninterruptible power supply detects the decay of the system power input to a first cross-over level.
    Type: Application
    Filed: November 23, 2011
    Publication date: May 23, 2013
    Applicant: SMART MODULAR TECHNOLOGIES, INC.
    Inventors: Jingying Shen, Robert Tower Frey, Kelvin Marino, Joshua Harris Brooks
  • Patent number: 8423724
    Abstract: A method for operating a dynamic back-up storage system includes: providing a high speed memory including a first rank memory device and subsequent ranks of memory devices; providing a non-volatile memory for saving data from the high speed memory; and providing a control logic unit for controlling access, of a central processing unit that executes a program, from the high speed memory including restoring the subsequent ranks of memory devices while the central processing unit is executing the program from the first rank memory device.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: April 16, 2013
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Kelvin Marino, Michael Rubino, Mike H. Amidi
  • Publication number: 20130039128
    Abstract: A method of operation of a non-volatile dynamic random access memory system including: accessing a dynamic random access memory; managing a delay-locked-loop control in the dynamic random access memory; sourcing timing inputs to the dynamic random access memory by a control logic unit with the delay-locked-loop control disabled including: selecting a back-up interface through a first multiplexer and a second multiplexer, asserting an on-board termination, and accessing data in the dynamic random access memory by the control logic unit at a lower frequency; and enabling a memory control interface by the control logic unit, with the delay-locked-loop control enabled including: selecting a host interface through the first multiplexer, the second multiplexer, or a combination thereof, disabling the on-board termination, and accessing the data in the dynamic random access memory by the memory control interface at a delay-locked-loop frequency.
    Type: Application
    Filed: August 11, 2011
    Publication date: February 14, 2013
    Applicant: SMART MODULAR TECHNOLOGIES, INC.
    Inventors: Mike H. Amidi, Kelvin Marino
  • Publication number: 20130036264
    Abstract: A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.
    Type: Application
    Filed: August 7, 2012
    Publication date: February 7, 2013
    Applicant: SMART Modular Technologies, Inc.
    Inventors: Hossein Amidi, Kelvin A. Marino, Satyadev Kolli
  • Patent number: 8250295
    Abstract: A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.
    Type: Grant
    Filed: January 5, 2004
    Date of Patent: August 21, 2012
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Hossein Amidi, Kelvin A. Marino, Satyadey Kolli
  • Publication number: 20120060009
    Abstract: A method for operating a dynamic back-up storage system includes: providing a high speed memory including a first rank memory device and subsequent ranks of memory devices; providing a non-volatile memory for saving data from the high speed memory; and providing a control logic unit for controlling access, of a central processing unit that executes a program, from the high speed memory including restoring the subsequent ranks of memory devices while the central processing unit is executing the program from the first rank memory device.
    Type: Application
    Filed: September 8, 2010
    Publication date: March 8, 2012
    Applicant: SMART MODULAR TECHNOLOGIES, INC.
    Inventors: Kelvin Marino, Michael Rubino, Mike H. Amidi
  • Publication number: 20110125966
    Abstract: A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.
    Type: Application
    Filed: October 11, 2010
    Publication date: May 26, 2011
    Applicant: SMART Modular Technologies, Inc.
    Inventors: Hossein Amidi, Kelvin A. Marino, Satyadev Kolli
  • Publication number: 20060118950
    Abstract: A memory module has a printed circuit board with connector pins. Several memory devices are mounted on the printed circuit board. An electrical circuit connects the memory devices to the connector pins such that the connector pins have multiple functionality based on the architecture of the memory devices used.
    Type: Application
    Filed: July 3, 2003
    Publication date: June 8, 2006
    Inventors: Hossein Amidi, Kelvin Marino, Satyadey Kolli
  • Publication number: 20060117152
    Abstract: A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.
    Type: Application
    Filed: January 5, 2004
    Publication date: June 1, 2006
    Inventors: Hossein Amidi, Kelvin Marino, Satyadey Kolli