Abstract: A method of and apparatus for improving the efficiency of a data processing system employing multiple dayclocks using the facilities which maintain coherency of the system's level cache memories. These efficiencies result from dedicating a separate individual dayclock to each of the multiple instruction processors within the data processing system thereby decreasing access time and user queuing. These individual dayclocks are each incremented at one microsecond intervals. However, these individual dayclocks require periodic synchronization to avoid system level time-tagging problems. This synchronization occurs at 20 microsecond intervals using the cache coherency maintenance hardware of the system.

Abstract: A system and method for controlling storage locks based on cache line ownership. Ownership of target data segments is acquired at a memory targeted by a first requesting device. A storage lock is enabled that prohibits requesting devices, other than the first requesting device, from acting on the target data segments during the time the targeted memory possesses ownership of the target data segments. A storage lock release signal is issued from the first requesting device to the targeted memory when exclusivity of the target data segments is no longer required at the first requesting device. In response, the storage lock at the targeted memory is released, thereby allowing other requesting devices to act on the target data segments.

Abstract: A system and method for controlling storage locks based on cache line ownership. Ownership of target data segments is acquired at a memory targeted by a first requesting device. A storage lock is enabled that prohibits requesting devices, other than the first requesting device, from acting on the target data segments during the time the targeted memory possesses ownership of the target data segments. A storage lock release signal is issued from the first requesting device to the targeted memory when exclusivity of the target data segments is no longer required at the first requesting device. In response, the storage lock at the targeted memory is released, thereby allowing other requesting devices to act on the target data segments.

Abstract: An improved directory-based, hierarchical memory system is disclosed that is capable of simultaneously processing multiple ownership requests initiated by a processor that is coupled to the memory. An ownership request is initiated on behalf of a processor to obtain an exclusive copy of memory data that may then be modified by the processor. In the data processing system of the preferred embodiment, multiple processors are each coupled to a respective cache memory. These cache memories are further coupled to a hierarchical memory structure including a main memory and one or more additional intermediate levels of cache memory. As is known in the art, copies of addressable portions of the main memory may reside in one or more of the cache memories within the hierarchical memory system. A memory directory records the location and status of each addressable portion of memory so that coherency may be maintained.

Abstract: A storage lock apparatus for a multiprocessor data processing system. The storage lock apparatus includes control for granting locks to different selectable portions of storage in parallel. In addition, acknowledgment from a remote lock controller is not required for a processor to obtain a lock on an address, even if the address for which the lock was requested is not local relative to the processor. Parallel priority queues are employed for parallel handling of storage lock functions and general storage operations, thereby reducing contention for priority between storage lock operations and general storage operations where there are no addressing conflicts.

Abstract: A glitch free clock switching circuit which produces a predictable and specifiable number of clock pulses to the system elements when switching between clock signals, even during full operation. In addition, the present invention has the capability of only switching between clocks at times that coincides with every Nth clock cycle. This is important in various types of computers systems including high reliability systems because it results in a clock switching circuit which can provide a clock signal which remains consistent throughout the computer system even in light of multiple hardware failures.

Abstract: A phase detecting system is provided for detecting when phase differences which occur between first and second clock pulses from a clock generator exceed acceptable tolerances, regardless of whether the first clock pulse leads the second clock pulse or the second clock pulse leads the first clock pulse. Two identical phase detectors are utilized each of which includes a phase detecting circuit, one group of signal delay elements that allow flip-flops in the phase detecting circuits time to set in order to detect the phase changes, and another group of signal delay elements coupled to the flip-flops which are set so the phase detecting circuit is capable of detecting the nominal phase delay times between the first and second clock pulses.

Abstract: A skew fault detection system for detecting clock skew between two clock phases utilizes a plurality of skew fault detection circuits each of which employs two D-type flip-flops. The clock terminals of both of these flip-flops are connected to one of the clock phases, and one of the clock phases is coupled to a delay circuit on the D input terminal of one of the flip-flops. The delay circuit is adjustable to correspond to the clock pulse delay that is inherent in the circuit that is being monitored to control the maximum amount of clock skew that is allowable before this flip-flop will set. If the clock skew exceeds this allowable time, a skew fault occurs and the flip-flop will set. The circuit compares the initiation of one clock phase against the initiation of the other clock phase and to determine when the initiation of one clock phase occurs earlier than the initiation of the other clock pulse by a time duration that exceeds a predetermined allowable skew amount of time.