Patents by Inventor Kelvin Tan Aik Boo

Kelvin Tan Aik Boo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230378128
    Abstract: A semiconductor package having a package substrate including an upper surface, a controller, a first die stack, and a second die stack. The controller, the first die stack, and the second die stack are at the upper surface. The first die stack includes a first shingled sub-stack and a first reverse-shingled sub-stack. The first die stack also includes a first bridging chip between the first shingled and reverse-shingled sub-stacks. The second die stack similarly includes a second shingled sub-stack and a second reverse-shingled sub-stack. The second die stack also includes a second bridging chip bonded to the top of the second reverse-shingled sub-stack. At least a portion of a bottom semiconductor die of the first reverse-shingled sub-stack is vertically aligned with a semiconductor die of the second shingled sub-stack and a semiconductor die of the second reverse-shingled sub-stack.
    Type: Application
    Filed: May 20, 2022
    Publication date: November 23, 2023
    Inventors: Seng Kim Ye, Kelvin Tan Aik Boo, Hong Wan Ng, Chin Hui Chong
  • Publication number: 20230369291
    Abstract: A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Inventors: Kelvin Tan Aik Boo, Seng Kim Ye, Chin Hui Chong, Hong Wan Ng
  • Publication number: 20230345639
    Abstract: An apparatus includes a primary layer of a substrate. The apparatus includes a secondary layer of the substrate having a first open area that extends through the secondary layer to an inner layer of the substrate. The apparatus includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes first component bond pads that are disposed on the inner layer and that are exposed via the first open area of the secondary layer.
    Type: Application
    Filed: June 28, 2023
    Publication date: October 26, 2023
    Inventors: Kelvin Tan Aik Boo, Chin Hui Chong, Seng Kim Ye, Hong Wan Ng, Hem P. Takiar
  • Publication number: 20230282588
    Abstract: Semiconductor device assemblies having redistribution structures, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor device assembly includes a substrate, a controller, and an interposer. The substrate has a top surface and a bottom surface. A cavity extends below the top surface. The controller has a first pin-out pattern. The interposer has a top surface with the first pin-out pattern that is directly connected to the controller and a bottom surface that has a second pin-out pattern. The interposer interconnects the first and second pin-out patterns, and the interposer and the second pin-out pattern are configured to be directly attached to a surface of the substrate in the cavity.
    Type: Application
    Filed: February 17, 2023
    Publication date: September 7, 2023
    Inventors: Kelvin Tan Aik Boo, Hong Wan Ng, Seng Kim Ye, Chin Hui Chong
  • Publication number: 20230282559
    Abstract: A semiconductor device assembly is provided. The assembly includes a substrate having an upper surface on which is disposed a first device contact, a keep-out region extending from a first side surface of the substrate to a second side surface of the substrate opposite the first, and at least one trace coupled to the first device contact and extending across the keep out region towards a third side surface of the substrate. The assembly further includes at least one semiconductor device disposed over the upper surface of the substrate and coupled to the first device contact. The keep-out region of the substrate is free from conductive structures other than the at least one trace.
    Type: Application
    Filed: March 3, 2022
    Publication date: September 7, 2023
    Inventors: Hong Wan Ng, Chin Hui Chong, Kelvin Tan Aik Boo, Seng Kim Ye
  • Patent number: 11723150
    Abstract: An apparatus includes a primary layer of a substrate that includes an open area that extends through the primary layer to an inner layer of the substrate. The apparatus includes a secondary layer of the substrate. The apparatus also includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes component bond pads that are disposed on the inner layer and that are exposed via the open area of the primary layer.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: August 8, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kelvin Tan Aik Boo, Chin Hui Chong, Seng Kim Ye, Hong Wan Ng, Hem P. Takiar
  • Patent number: 11710722
    Abstract: A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: July 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kelvin Tan Aik Boo, Seng Kim Ye, Chin Hui Chong, Hong Wan Ng
  • Patent number: 11688662
    Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments the semiconductor devices include a package substrate, a controller die carried by the package substrate and a spacer carried by the package substrate spaced apart from the controller die. A thermally conductive material can be carried by an upper surface of the controller die and establish a thermal path extending from the upper surface of the controller die to the package substrate. The thermal path can reach the package substrate at a position horizontally between the controller die and the spacer. The semiconductor device can also include one or more dies at least partially carried by the spacer and at least partially above the controller die and the thermally conductive material. Each of the one or more dies is thermally insulated from the thermally conductive material, for example by a thermal adhesive layer between the two.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ling Pan, Sook Har Leong, Kelvin Tan Aik Boo
  • Publication number: 20230066375
    Abstract: Semiconductor devices including thermally conductive structures are disclosed herein. A heat transfer structure may be thermally coupled to a semiconductor device and directly attached to a signaling layer of a substrate. The heat transfer structure may be configured to remove thermal energy from the semiconductor device and transfer at least a portion of the removed thermal energy directly into the signaling layer for dissipation within the substrate, for transfer through the substrate and out of a corresponding apparatus, or a combination thereof.
    Type: Application
    Filed: August 26, 2021
    Publication date: March 2, 2023
    Inventors: Kelvin Tan Aik Boo, Hong Wan Ng, Seng Kim Ye, Chin Hui Chong
  • Publication number: 20230069476
    Abstract: Semiconductor devices having three-dimensional bonding schemes and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device includes a package substrate, a stack of semiconductor dies carried by the package substrate, and an interconnect module carried by the package substrate adjacent the stack of semiconductor dies. The stack of semiconductor dies can include a first die carried by the package substrate and a second die carried by the first die. Meanwhile, the interconnect module can include at least a first tier and a second tier. The first tier can be carried by and electrically coupled to the package substrate, and the second tier can be carried by and electrically coupled to the first tier. In turn, the second die can be electrically coupled to the second tier.
    Type: Application
    Filed: February 3, 2022
    Publication date: March 2, 2023
    Inventors: Kelvin Tan Aik Boo, Hong Wan Ng, Seng Kim Ye, Chin Hui Chong
  • Publication number: 20230061803
    Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments the semiconductor devices include a package substrate, a controller die carried by the package substrate and a spacer carried by the package substrate spaced apart from the controller die. A thermally conductive material can be carried by an upper surface of the controller die and establish a thermal path extending from the upper surface of the controller die to the package substrate. The thermal path can reach the package substrate at a position horizontally between the controller die and the spacer. The semiconductor device can also include one or more dies at least partially carried by the spacer and at least partially above the controller die and the thermally conductive material. Each of the one or more dies is thermally insulated from the thermally conductive material, for example by a thermal adhesive layer between the two.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Ling Pan, Sook Har Leong, Kelvin Tan Aik Boo
  • Publication number: 20230056648
    Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.
    Type: Application
    Filed: November 7, 2022
    Publication date: February 23, 2023
    Inventors: Hong Wan Ng, Chin Hui Chong, Hem P. Takiar, Seng Kim Ye, Kelvin Tan Aik Boo
  • Patent number: 11562987
    Abstract: Semiconductor devices having multiple substrates and die stacks, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor device includes a package substrate, and a first die stack mounted on the package substrate and including a plurality of first memory dies. The device can include a substrate mounted on the first die stack, the substrate including a plurality of routing elements. The device can also include a second die stack mounted on the substrate, the second die stack including a plurality of second memory dies. The device can further include a controller die mounted on the substrate. The controller die can be configured to communicate with the second die stack via the routing elements of the substrate. The device can include a mold material encapsulating the first die stack, the second die stack, the substrate, and the controller die.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Chin Hui Chong, Hong Wan Ng, Hem P. Takiar, Seng Kim Ye, Kelvin Tan Aik Boo
  • Patent number: 11527459
    Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to first and second distances between electrical contacts of the first and second surface-mount capacitors.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: December 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hong Wan Ng, Chin Hui Chong, Hem P. Takiar, Seng Kim Ye, Kelvin Tan Aik Boo
  • Publication number: 20220352052
    Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of first and second surface-mount capacitors.
    Type: Application
    Filed: April 28, 2021
    Publication date: November 3, 2022
    Inventors: Hong Wan Ng, Chin Hui Chong, Hem P. Takiar, Seng Kim Ye, Kelvin Tan Aik Boo
  • Publication number: 20220336419
    Abstract: A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.
    Type: Application
    Filed: April 16, 2021
    Publication date: October 20, 2022
    Inventors: Kelvin Tan Aik Boo, Seng Kim Ye, Chin Hui Chong, Hong Wan Ng
  • Publication number: 20220336417
    Abstract: Semiconductor devices having multiple substrates and die stacks, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor device includes a package substrate, and a first die stack mounted on the package substrate and including a plurality of first memory dies. The device can include a substrate mounted on the first die stack, the substrate including a plurality of routing elements. The device can also include a second die stack mounted on the substrate, the second die stack including a plurality of second memory dies. The device can further include a controller die mounted on the substrate. The controller die can be configured to communicate with the second die stack via the routing elements of the substrate. The device can include a mold material encapsulating the first die stack, the second die stack, the substrate, and the controller die.
    Type: Application
    Filed: April 16, 2021
    Publication date: October 20, 2022
    Inventors: Chin Hui Chong, Hong Wan Ng, Hem P. Takiar, Seng Kim Ye, Kelvin Tan Aik Boo
  • Publication number: 20220208744
    Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device is an assembly that includes a package substrate having a front side and a backside opposite the front side. A controller die with a first longitudinal footprint can be attached to the front side of the package substrate. A passive electrical component is also attached to the front side of the package substrate. A stack of semiconductor dies can be attached to the controller die and the passive electrical component. The stack of semiconductor dies has a second longitudinal footprint greater than the first longitudinal footprint in at least one dimension. The controller die and the passive electrical component are positioned at least partially within the second longitudinal footprint, thereby at least partially supporting the stack of semiconductor dies.
    Type: Application
    Filed: December 29, 2020
    Publication date: June 30, 2022
    Inventors: Hong Wan Ng, Kelvin Tan Aik Boo, Chin Hui Chong, Hem P. Takiar, Seng Kim Ye
  • Patent number: 11282811
    Abstract: An apparatus includes an integrated circuit and a substrate coupled to the integrated circuit. The substrate includes a primary layer having a first surface that is a first external surface of the substrate. The primary layer includes an open area that extends through the primary layer to an inner layer of the substrate. The substrate includes a secondary layer. The inner layer is located between the primary layer and the secondary layer. The inner layer includes a third surface that is orientated approximately parallel to the first surface of the primary layer. A portion of the third surface of the inner layer is exposed via the open area of the primary layer. A first plurality of wire bond pads are disposed on the portion of the third surface of the inner layer that is exposed via the open area of primary layer.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kelvin Tan Aik Boo, Chin Hui Chong, Seng Kim Ye, Hong Wan Ng, Hem P. Takiar
  • Publication number: 20220078915
    Abstract: An apparatus includes a primary layer of a substrate that includes an open area that extends through the primary layer to an inner layer of the substrate. The apparatus includes a secondary layer of the substrate. The apparatus also includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes component bond pads that are disposed on the inner layer and that are exposed via the open area of the primary layer.
    Type: Application
    Filed: September 4, 2020
    Publication date: March 10, 2022
    Inventors: Kelvin Tan Aik Boo, Chin Hui Chong, Seng Kim Ye, Hong Wan Ng, Hem P. Takiar