Abstract: Disclosed is a system and method for performing direct memory characterization of memory cells in a memory array using peripheral transistors. A memory array is fabricated using a mask layer defining routing for a set of first stage periphery transistors electrically connected to the word lines of the memory array. A revised mask is used for defining a different routing for a set of second stage periphery transistors including different characteristics than the first stage periphery transistors. Testing is conducted by applying a simulated Erase signal to the nonvolatile memory cells and determining which cells are erased. Based on this test, certain characteristics of the first and/or second stage periphery transistors can be identified that provide improved conditions for the nonvolatile memory cells. A product chip can be manufactured using modified versions of the first stage periphery transistors that incorporate the characteristics that provide the improved condition(s).

Abstract: A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed.

Abstract: A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed.

Abstract: A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed.

Abstract: A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed.

Abstract: A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed.

Abstract: A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed.

Abstract: A method for avoiding current leakage at the shallow trench isolation edge in a border-less contact process is described. Trenches are etched into a semiconductor substrate. An etch stop liner layer is deposited within the trenches and etched back to leave the etch stop liner layer only on sidewalls of the trenches. The trenches are filled with an isolation layer overlying the liner sidewalls and polished back to leave the isolation layer only within the trenches. Semiconductor device structures, including source and drain junctions, are formed in the active areas. An interlevel dielectric layer is deposited over the device structures. Border-less contact openings are etched through the ILD wherein the liner sidewalls act as an etch stop thereby preventing leakage of the source and drain junctions. The contact openings are filled with a conducting layer wherein the liner sidewalls act as a diffusion barrier to the conducting layer.