Abstract: Disclosed by present disclosure are a self-powered power supply drive circuit and a self-powered power supply drive chip. The self-powered power supply drive circuit includes a charging detection circuit, a current sampling switch tube, a charging switch tube, a sampling circuit and a control circuit. The drive tube and current sampling switch tube, which are connected in series, are connected between the input power supply and the ground. The current sampling switch tube is switched off and the charging switch tube is switched on during the pre-switching-off stage, such that the current which flows through the drive tube during the pre-switching-off stage is used to charge the energy storage circuit. The charging time is in the pre-switching-off stage, which never affects the normal switching cycle of the drive tube itself and the normal output of energy. Moreover, this way of charging does not require any additional auxiliary coil winding.

Abstract: Disclosed is a power supply drive circuit, chip and method. In each switching-on cycle, the charging demand is considered. If the current switching-on cycle requires charging, after the drive tube is completely switched on in the current switching-on cycle, the sampling switch tube is switched off and the charging switch tube is switched on for using a small current which flows through the drive tube in the early stage of the switching-on cycle for charging. In the later stage of the current switching-on cycle, the sampling switch tube is switched on and the charging switch tube is switched off, such that the current outputted by the drive tube flows through the current sampling switch tube according to the normal path. In this way, the power supply voltage never changes with the output power, the cumbersome design and debugging of the power supply circuit are avoid.

Abstract: Disclosed by present disclosure are a Darlington transistor drive circuit, a Darlington transistor drive method and a switching power supply management chip. In this embodiment, the Darlington transistor is driven sectionally. At the beginning of the switching-on cycle, the driving of the primary transistor is not started temporarily, instead the drive source is used to drive the secondary transistor. After the secondary transistor is completely switched on, the drive source of the secondary transistor is switched off and the drive source of the primary transistor is switched on to drive the Darlington transistor. The primary and secondary transistor have been completely switched on, and the drive current of the secondary transistor never depend on the primary transistor, so the voltage at the input terminal of the secondary transistor can be smaller than the voltage at the control terminal of the secondary transistor. Such that the switching-on power loss is reduced.

Abstract: An adding circuit for multi-channel signals and an implementation method thereof are disclosed. The adding circuit for multi-channel signals includes an operational amplifier, a plurality of charge and discharge circuits, a charge transfer circuit, a switch sequence and a control circuit. In this disclosure, the duty cycle of each charge and discharge circuit and the charge transfer circuit can be programmed and preset according to the actual needs, which is not only suitable for the static voltage adding circuit, but also suitable for the dynamic voltage adding circuit. When there are multi-channel signals, the output interference caused by individual signals can be prevented. The area of the adding circuit can be greatly reduced. The adding circuit can be IP-based, controlled by programing and presetting a variety of combined adding algorithms, so the chip cost can be saved and a wide applicability in detection and monitoring can be provided.

Abstract: A higher voltage switching circuit based on a standard process limits the lowest applied voltage to an intermediate voltage between the higher voltage and ground, instead of ground. In this way, the maximum electric field across the gate dielectric is greatly reduced. In additional the use of p-type triple well also reduces junction breakdown in some embodiments. This concept is also valid in the case where the high voltage is negative, in which case the intermediate voltage is also negative.

Abstract: A triple poly nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor operates as a charge injector. The charge injector may provide electrons for substrate hot electron injection of electrons onto the floating gate for programming. The select transistor may include a gate formed as a self-aligned sidewall spacer on said sense transistor.

Abstract: A triple poly nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor operates as a charge injector. The charge injector may provide electrons for substrate hot electron injection of electrons onto the floating gate for programming. The select transistor may include a gate formed as a self-aligned sidewall spacer on said sense transistor.

Abstract: A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A pair of sources for a pair of cells on adjacent word lines each acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor of one cell operates as a charge injector for the other cell. The charge injector provides carriers for substrate hot carrier injection onto a floating gate.

Abstract: A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A pair of sources for a pair of cells on adjacent word lines each acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor of one cell operates as a charge injector for the other cell. The charge injector provides carriers for substrate hot carrier injection onto a floating gate.

Abstract: A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A pair of sources for a pair of cells on adjacent word lines each acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor of one cell operates as a charge injector for the other cell. The charge injector provides carriers for substrate hot carrier injection onto a floating gate.