Abstract: The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

Abstract: The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

Abstract: A method is described to partition the memory of application-specific hardware compiled from a software program. Applying the invention generates multiple small memories that need not be kept coherent and are defined over a specific region of the program. The invention creates application specific hardware which preserves the memory image and addressing model of the original software program. The memories are dynamically initialized and flushed at the entries and exits of the program region they are defined in.

Abstract: A parallel hypervisor system for virtualizing application-specific supercomputers is disclosed. The hypervisor system comprises (a) at least one software-virtual hardware pair consisting of a software application, and an application-specific virtual supercomputer for accelerating the said software application, wherein (i) The virtual supercomputer contains one or more virtual tiles; and (ii) The software application and the virtual tiles communicate among themselves with messages; (b) One or more reconfigurable physical tiles, wherein each virtual tile of each supercomputer can be implemented on at least one physical tile, by configuring the physical tile to perform the virtual tile's function; and (c) A scheduler implemented substantially in hardware, for parallel pre-emptive scheduling of the virtual tiles on the physical tiles.

Abstract: The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

Abstract: A method is described to partition the memory of application-specific hardware compiled from a software program. Applying the invention generates multiple small memories that need not be kept coherent and are defined over a specific region of the program. The invention creates application specific hardware which preserves the memory image and addressing model of the original software program. The memories are dynamically initialized and flushed at the entries and exits of the program region they are defined in.

Abstract: According to a first aspect of the invention there is provided a method for profiling computer program executions in a computer processing system having a processor and a memory hierarchy. The method includes the step of executing a computer program. Profile counts are stored in a memory array for events associated with the execution of the computer program. The memory array is separate and distinct from the memory hierarchy so as to not perturb normal operations of the memory hierarchy.

Abstract: Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, an arrangement for speculatively accessing a storage structure with a storage access instruction extended by the extending arrangement, and an arrangement for reverting to the arrangement for inputting an address if the load/store operand is not in the speculative location.

Abstract: Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, an arrangement for speculatively accessing a storage structure with a storage access instruction extended by the extending arrangement, and an arrangement for reverting to the arrangement for inputting an address if the load/store operand is not in the speculative location.

Abstract: In a dynamically compiling computer system, a system and method for efficiently transferring control from execution of an instruction in a first representation to a second representation of the instruction is disclosed. The system and method include the setting of a tag for entry points of each instruction in a first representation that has been translated to a second representation. The tag is stored in memory in association with each such instruction. When a given instruction in a first representation is to be executed, the tag is examined, and if it indicates that a translated version of the instruction has previously been generated, control is passed to execution of the instruction in the second representation. The second representation can be a different instruction set representation, or an optimized representation in the same instruction set as the original instruction.

Abstract: Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, an arrangement for speculatively accessing a storage structure with a storage access instruction extended by the extending arrangement, and an arrangement for reverting to the arrangement for inputting an address if the load/store operand is not in the speculative location.

Abstract: Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, an arrangement for speculatively accessing a storage structure with a storage access instruction extended by the extending arrangement, and an arrangement for reverting to the arrangement for inputting an address if the load/store operand is not in the speculative location.

Abstract: Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, an arrangement for speculatively accessing a storage structure with a storage access instruction extended by the extending arrangement, and an arrangement for reverting to the arrangement for inputting an address if the load/store operand is not in the speculative location.

Abstract: Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, an arrangement for speculatively accessing a storage structure with a storage access instruction extended by the extending arrangement, and an arrangement for reverting to the arrangement for inputting an address if the load/store operand is not in the speculative location.

Abstract: In a dynamically compiling computer system, a system and method for efficiently transferring control from execution of an instruction in a first representation to a second representation of the instruction is disclosed. The system and method include the setting of a tag for entry points of each instruction in a first representation that has been translated to a second representation. The tag is stored in memory in association with each such instruction. When a given instruction in a first representation is to be executed, the tag is examined, and if it indicates that a translated version of the instruction has previously been generated, control is passed to execution of the instruction in the second representation. The second representation can be a different instruction set representation, or an optimized representation in the same instruction set as the original instruction.

Abstract: There is provided a method for reordering and renaming memory references in a multiprocessor computer system having at least a first and a second processor. The first processor has a first private cache and a first buffer, and the second processor has a second private cache and a second buffer. The method includes the steps of, for each of a plurality of gated store requests received by the first processor to store a datum, exclusively acquiring a cache line that contains the datum by the first private cache, and storing the datum in the first buffer. Upon the first buffer receiving a load request from the first processor to load a particular datum, the particular datum is provided to the first processor from among the data stored in the first buffer based on an in-order sequence of load and store operations.

Abstract: In a computer capable of executing a superscalar and a very long instruction word instruction wherein the computer has compiled a number of primitive operations that can be executed in parallel into a single instruction having multiple parcels and each of the parcels correspond to an operation, the invention is an improved instruction cache to store all potential subsequent instructions and a method to select the subsequent instruction when several possible branches of execution are probable and must be evaluated. All branch conditions and all addresses of potential subsequent instructions of an instruction are replicated and stored in the instruction cache. All potential subsequent instructions are stored in the same block of the instruction cache having the same next address; individual instructions are identified by the replicated offset addresses. Further the instruction cache is divided into minicaches, each minicache to store one parcel, which allows rapid autonomous execution of each parcel.

Abstract: CPU overhead is minimized through tracking speculative exceptions (202) for later processing during exception resolution (204) including pointing to the addresses of these speculative instructions, and resolving (204) these exceptions by correcting (206) what caused the exception and re-executing (208) the instructions which are known to be in a taken path. Tracking speculative exceptions has two components which use an exception bit which is set in response to an exception condition (213). The invention tracks an original speculative exception which occurs when a speculative instruction whose operand(s) do not have any exception bits set encounters an exception condition. Speculative exception resolution is triggered when a non-speculative instruction--which is in the taken path of a conditional branch--uses an operand from a register having its exception bit set. The presence of an exception condition and a non-speculative instruction yields an exception signal (220) to exception resolution (204).

Abstract: An instruction cache design which converts a sequential instruction stream into a compound format in the instruction cache. The conversion from sequential instructions to compound instructions is performed by an instruction stream interpreter unit (ISU), which is placed between the instruction cache and main memory. The conversion process is performed when an instruction cache miss occurs. Each line in the instruction cache contains a single compound instruction. The format of this compound instruction is transparent to programmers and will vary depending on the number of execution units which are to be supported.