Abstract: It is an object of one or more embodiments of the present disclosure to provide a single-inductor dual-output (SIDO), or single-inductor multiple-output (SIMO), Buck switching converter which can supply opposite polarity current to its outputs, through an inductor. It is a further object of one or more embodiments, when one output has an overshoot and the other output is below a reference, to enable discharging the overshoot output to the other output, resulting in a significant charge recycling and considerable increase in power efficiency. Still further, it is an object of one or more embodiments to improve output voltage ripple, as both outputs are being supplied at the same time, compared to prior art SIDO operation, where only one output is supplied for a given phase.

Abstract: It is an object of one or more embodiments of the present disclosure to provide a single-inductor dual-output (SIDO), or single-inductor multiple-output (SIMO), Buck switching converter which can supply opposite polarity current to its outputs, through an inductor. It is a further object of one or more embodiments, when one output has an overshoot and the other output is below a reference, to enable discharging the overshoot output to the other output, resulting in a significant charge recycling and considerable increase in power efficiency. Still further, it is an object of one or more embodiments to improve output voltage ripple, as both outputs are being supplied at the same time, compared to prior art SIDO operation, where only one output is supplied for a given phase.

Abstract: DC-DC voltage regulators for converting an input voltage into one or more output voltages and methods for operating such voltage regulators are described. The voltage regulator may have a high side switching device coupled between the input port and a first intermediate node. The voltage regulator may have an inductive element having one port coupled to the first intermediate node and may have a capacitive element having two ports, coupled between the first intermediate node and a second intermediate node, with its one port coupled to the first intermediate node. The voltage regulator may have a charging switching device coupled between the other port of the capacitive element and a predetermined voltage level, for charging the capacitive element when the high side switching device and the charging switching device are both in an ON state.

Abstract: DC-DC voltage regulators for converting an input voltage into one or more output voltages and methods for operating such voltage regulators are described. The voltage regulator may have a high side switching device coupled between the input port and a first intermediate node. The voltage regulator may have an inductive element having one port coupled to the first intermediate node and may have a capacitive element having two ports, coupled between the first intermediate node and a second intermediate node, with its one port coupled to the first intermediate node. The voltage regulator may have a charging switching device coupled between the other port of the capacitive element and a predetermined voltage level, for charging the capacitive element when the high side switching device and the charging switching device are both in an ON state.

Abstract: A solution is provided for suppressing audio noise in a DC-DC switching converter. A means for limiting the minimum switching frequency of a pulse-frequency modulation (PFM) control is described. A first order gm amplifier dissipates the excess energy added to the inductor, when magnetizing at faster rate than the native PFM. A higher resistance, low-side scaled switch helps reduce wasted energy losses. The low-side scaled switch reduces the rise in the inductor current during magnetization, and hence keeps efficiency up at low loads, when the PFM minimum switching frequency is active.

Abstract: A solution is provided for suppressing audio noise in a DC-DC switching converter. A means for limiting the minimum switching frequency of a pulse-frequency modulation (PFM) control is described. A first order gm amplifier dissipates the excess energy added to the inductor, when magnetizing at faster rate than the native PFM. A higher resistance, low-side scaled switch helps reduce wasted energy losses. The low-side scaled switch reduces the rise in the inductor current during magnetization, and hence keeps efficiency up at low loads, when the PFM minimum switching frequency is active.

Abstract: Circuits and methods to achieve a hysteretic buck-boost converter system, separating buck and boost pulses based on monitoring a difference between the output voltage of the buck-boost converter and a reference voltage (error voltage) or alternatively based on monitoring additionally coil current or load current or both currents have been disclosed. The performance of the buck-boost converter can be further improved by using an optional output voltage change block monitoring if the output voltage rises or falls. The buck-boost converter disclosed has a very simple topology without a modulator block, which is regulating the duty cycle and without frequency compensation.

Abstract: A node that stores a charge is discharged in two phases, starting with a current controlled phase where a current mirror sink controls the current sunk from the node, and then moving to a second phase where a resistive discharge is provided. A pull down device such as a transistor switches from its saturation mode in the first phase to its linear mode in the second phase. a discharge circuit implementing this method provides optimized area and control for the discharge process as compared with approaches that rely solely on current mirroring or resistive discharging.

Abstract: The disclosure describes an adaptive technique for generating minimum dead time in a DC-DC switching power converter, while ensuring no short circuit losses occur, resulting in efficiency improvement of the switching converter. In addition, this adaptive scheme makes sure that even the ambient conditions of the switching converter give the best decision at the ON/OFF timings of the switches. Body diode conduction feedback is detected, with reduced process sensitivity, and an algorithm is disclosed that finds the minimum dead time for a given load current, temperature, and process conditions.

Abstract: Circuits and methods to achieve a hysteretic buck-boost converter system, separating buck and boost pulses based on monitoring a difference between the output voltage of the buck-boost converter and a reference voltage (error voltage) or alternatively based on monitoring additionally coil current or load current or both currents have been disclosed. The performance of the buck-boost converter can be further improved by using an optional output voltage change block monitoring if the output voltage rises or falls. The buck-boost converter disclosed has a very simple topology without a modulator block, which is regulating the duty cycle and without frequency compensation.

Abstract: The disclosure describes an adaptive technique for generating minimum dead time in a DC-DC switching power converter, while ensuring no short circuit losses occur, resulting in efficiency improvement of the switching converter. In addition, this adaptive scheme makes sure that even the ambient conditions of the switching converter give the best decision at the ON/OFF timings of the switches. Body diode conduction feedback is detected, with reduced process sensitivity, and an algorithm is disclosed that finds the minimum dead time for a given load current, temperature, and process conditions.

Abstract: An average load current calculator circuit configured for determining an average load current within an at least one phase switch mode power converter (SMPC) having at least one peak/valley detector receives an inductor current sense signal and determines and holds a peak or valley amplitude of the inductor current sense signal. A current corrector circuit receives an input voltage and an output voltage of the SMPC and an inductance value of the inductor of the SMPC for determining an average correction current of the peak or valley amplitude of the current sense. An average current generator receives the peak or valley amplitude of the current sense signal and the average correction current for determining the instantaneous average load current within a switch mode power converter (SMPC) by additively combining the peak or valley amplitude of the current sense signal and the average correction current.

Abstract: A circuit and method for providing an improved efficiency for a DCDC converter. A power converter, comprising a buck converter comprising an adaptive output, an adaptive transconductance block configured to evaluate resistive power terms, a multiplier block configured to provide capacitive power terms, and a comparator configured to compare resistive power and capacitive power terms for determining the selection of the branches of said adaptive output. The method for improved efficiency includes providing a switching converter with an adaptive output stage comprising the steps of providing a switching converter, evaluate capacitive power loss, evaluate resistive power loss, compare capacitive power loss and resistive power loss, and lastly adapting the output stage size.

Abstract: An adaptive duty cycle limiting circuit is used with a switching DC-to-DC converter for preventing the duty cycle entering a region of operation having negative gain. The adaptive duty cycle limiting circuit includes a duty cycle ramp signal generator, a voltage source for providing a voltage having a fractional value of an input voltage source, and a comparator that compares the duty cycle ramp signal with the fractional value of the input voltage source. When the voltage level of the duty cycle ramp signal is less than the fractional value of the voltage source, a cycle limit signal is activated and communicated to a switching control circuit to adjust the duty cycle of the switching DC-to-DC converter to prevent the duty cycle entering the region of operation where the gain of the switching DC-to-DC converter becomes negative.

Abstract: A switching DC-to-DC converter has an adaptive duty cycle limiting circuit with an inductor current sensor to generate a sense signal indicative of magnitude of the inductor current. A replica signal is generated from the sense signal and transferred through a replica parasitic resistance circuit. A differential voltage is developed across the replica parasitic resistances and compared with a maximum limit voltage level. The maximum limit voltage level is indicates that a gain level of the switching DC-to-DC converter has decreased even though the duty cycle has increased. A duty cycle limit signal is generated and transferred to disable a switch in a switching circuit for limiting the duty cycle of the switching DC-to-DC converter, when the gain level has decreased such that the switching DC-to-DC converter does not enter a region where the gain of the switching DC-to-DC converter has a negative slope.

Abstract: An adaptive duty cycle limiting circuit is used with a switching DC-to-DC converter for preventing the duty cycle entering a region of operation having negative gain. The adaptive duty cycle limiting circuit includes a duty cycle ramp signal generator, a voltage source for providing a voltage having a fractional value of an input voltage source, and a comparator that compares the duty cycle ramp signal with the fractional value of the input voltage source. When the voltage level of the duty cycle ramp signal is less than the fractional value of the voltage source, a cycle limit signal is activated and communicated to a switching control circuit to adjust the duty cycle of the switching DC-to-DC converter to prevent the duty cycle entering the region of operation where the gain of the switching DC-to-DC converter becomes negative.

Abstract: A first transconductance cell having a differential input voltage ?V1 and a forced output current ?I1, has a bias set by a feedback loop. A second transconductance cell having a differential input voltage ?V2 and using the same biasing as the first cell has analytically identical transconductance. The second transconductance cell produces an output current ?I2 dependent on the product of the output current ?I1 of the first transconductance cell and the quotient of the second differential input voltage ?V2, and the first differential input voltage ?V1. The adaptive transconductance cells can be used to generate mathematic functions such as multiplication and division.

Abstract: A switching DC-to-DC converter has an adaptive duty cycle limiting circuit with an inductor current sensor to generate a sense signal indicative of magnitude of the inductor current. A replica signal is generated from the sense signal and transferred through a replica parasitic resistance circuit. A differential voltage is developed across the replica parasitic resistances and compared with a maximum limit voltage level. The maximum limit voltage level is indicates that a gain level of the switching DC-to-DC converter has decreased even though the duty cycle has increased. A duty cycle limit signal is generated and transferred to disable a switch in a switching circuit for limiting the duty cycle of the switching DC-to-DC converter, when the gain level has decreased such that the switching DC-to-DC converter does not enter a region where the gain of the switching DC-to-DC converter has a negative slope.

Abstract: A circuit and method for providing an improved efficiency for a DCDC converter. A power converter, comprising a buck converter comprising an adaptive output, an adaptive transconductance block configured to evaluate resistive power terms, a multiplier block configured to provide capacitive power terms, and a comparator configured to compare resistive power and capacitive power terms for determining the selection of the branches of said adaptive output. The method for improved efficiency includes providing a switching converter with an adaptive output stage comprising the steps of providing a switching converter, evaluate capacitive power loss, evaluate resistive power loss, compare capacitive power loss and resistive power loss, and lastly adapting the output stage size.

Abstract: A first transconductance cell having a differential input voltage ?V1 and a forced output current ?I1, has a bias set by a feedback loop. A second transconductance cell having a differential input voltage ?V2 and using the same biasing as the first cell has analytically identical transconductance. The second transconductance cell produces an output current ?I2 dependent on the product of the output current ?I1 of the first transconductance cell and the quotient of the second differential input voltage ?V2, and the first differential input voltage ?V1. The adaptive transconductance cells can be used to generate mathematic functions such as multiplication and division.