Abstract: The present disclosure generally relates to a buried channel semiconductor device that includes one or more energy barrier modulation regions. In an example, a device includes a source/drain region, an energy barrier modulation region, a channel covering surface region, and a gate structure. The source/drain region is in a doped region in a semiconductor substrate that has an upper surface. The energy barrier modulation and channel covering surface regions are in the doped region and at the upper surface. The gate structure is over the upper surface. The energy barrier modulation and channel covering surface regions underlie the gate structure. The energy barrier modulation region is laterally between the source/drain and channel covering surface regions. The doped and energy barrier modulation regions are doped with a first conductivity type, and the source/drain and channel covering surface regions are doped with a second conductivity type opposite from the first conductivity type.

Abstract: A method and system for minimizing bit stress in a non-volatile memory during an erase operation are disclosed, which can increase the absolute value of the gate voltage of a memory cell incrementally with each subsequent high voltage erase pulse during the erase operation, instead of ramping up the absolute value of the gate voltage completely during each pulse. Also, each high voltage pulse can be conditioned so that its leading edge does not transition too quickly. Furthermore, a state machine for a flash memory device is disclosed, which can perform, among other things, the erase functions and/or algorithms used for the flash memory.

Abstract: A system for testing and adjusting threshold voltages in flash EEPROMs is disclosed. The system includes a memory cell array (5) comprising a plurality of cell columns. Each cell column includes a plurality of memory cells (10). Each memory cell (10) has a control gate terminal (14), a drain terminal (12) and a source terminal 11. A control system comprising a wordline decoder (16), a column decoder (19) and a microprocessor (21) applies selected voltages to the respective terminals of the memory cells (10), and selects one of the plurality of cell columns for compaction verification. A detector (30) determines whether any one of the memory cells (10) of the selected cell column has a threshold voltage below a predetermined positive voltage, and supplies an output signal to the control system. The control system increases respective threshold voltages of the memory cells (10) of the selected cell column in response to the output signal of the detector (30).