Abstract: Methods of forming semiconductor devices including an air gap extending through at least one metal layer, and the semiconductor device so formed, are disclosed. The air gap has a lower portion that contacts a silicide layer over a gate body of a transistor gate and has an inverted T-shape over the gate body. The air gap reduces the capacitance between a transistor gate in a device layer and adjacent wires and vias used to contact the source and drain of the transistor.

Abstract: A method for forming a thin film resistor (TFR) without via penetration and the resulting device are provided. Embodiments include forming a first ILD over a substrate; forming a second ILD over the first ILD; forming a first metal layer in the second ILD; forming a first nitride layer over the second ILD and the first metal layer; forming a third ILD over the first nitride layer; forming vias through the third ILD and the first nitride layer, coupled to the first metal layer; forming a TFR layer over two of the vias and the third ILD between the two vias; forming a second nitride layer over the TFR layer and the third ILD; forming a fourth ILD over the second nitride layer; and forming a second metal layer in the fourth ILD and the second nitride layer.

Abstract: A metal oxide semiconductor varactor includes an active area doped well that is disposed within a semiconductor substrate and a gate structure including a first portion that extends over the active area doped well and a second portion that extends over the semiconductor substrate outside of the active area doped well. The varactor further includes at least one active area contact structure formed in physical and electrical connection with the active area doped well, in a three-sided contact-landing area of the active area doped well. Still further, the varactor includes a gate contact structure that is formed in physical and electrical contact with the gate structure in the second portion of the gate structure such that the gate contact structure overlies the semiconductor substrate outside of the active area doped well.

Abstract: A method for forming a thin film resistor (TFR) without via penetration and the resulting device are provided. Embodiments include forming a first ILD over a substrate; forming a second ILD over the first ILD; forming a first metal layer in the second ILD; forming a first nitride layer over the second ILD and the first metal layer; forming a third ILD over the first nitride layer; forming vias through the third ILD and the first nitride layer, coupled to the first metal layer; forming a TFR layer over two of the vias and the third ILD between the two vias; forming a second nitride layer over the TFR layer and the third ILD; forming a fourth ILD over the second nitride layer; and forming a second metal layer in the fourth ILD and the second nitride layer.

Abstract: A metal oxide semiconductor varactor includes an active area doped well that is disposed within a semiconductor substrate and a gate structure including a first portion that extends over the active area doped well and a second portion that extends over the semiconductor substrate outside of the active area doped well. The varactor further includes at least one active area contact structure formed in physical and electrical connection with the active area doped well, in a three-sided contact-landing area of the active area doped well. Still further, the varactor includes a gate contact structure that is formed in physical and electrical contact with the gate structure in the second portion of the gate structure such that the gate contact structure overlies the semiconductor substrate outside of the active area doped well.

Abstract: Embodiments of a method for forming a device using test structures are presented. The method includes providing a wafer with a device layer. The device layer includes a main device region and a perimeter region. The device layer is patterned with active and test patterns. Test patterns include dummy patterns disposed in a test device area. The wafer is processed to form at least one test device disposed in the perimeter region and one or more active devices disposed in the main device region. The test device determines a design window of the one or more active devices. Additional processing is performed to complete forming the device.

Abstract: Embodiments of a method for forming a device using test structures are presented. The method includes providing a wafer with a device layer. The device layer includes a main device region and a perimeter region. The device layer is patterned with active and test patterns. Test patterns include dummy patterns disposed in a test device area. The wafer is processed to form at least one test device disposed in the perimeter region and one or more active devices disposed in the main device region. The test device determines a design window of the one or more active devices. Additional processing is performed to complete forming the device.