Patents by Inventor Kemel AYGUN

Kemel AYGUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230352412
    Abstract: A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.
    Type: Application
    Filed: July 12, 2023
    Publication date: November 2, 2023
    Inventors: Yidnekachew S. MEKONNEN, Kemel AYGUN, Ravindranath V. MAHAJAN, Christopher S. BALDWIN, Rajasekaran SWAMINATHAN
  • Patent number: 11742293
    Abstract: A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: August 29, 2023
    Assignee: Intel Corporation
    Inventors: Yidnekachew S. Mekonnen, Kemel Aygun, Ravindranath V. Mahajan, Christopher S. Baldwin, Rajasekaran Swaminathan
  • Publication number: 20190363049
    Abstract: A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.
    Type: Application
    Filed: March 22, 2017
    Publication date: November 28, 2019
    Inventors: Yidnekachew S. MEKONNEN, Kemel AYGUN, Ravindranath V. MAHAJAN, Christopher S. BALDWIN, Rajasekaran SWAMINATHAN
  • Publication number: 20190252322
    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.
    Type: Application
    Filed: June 30, 2016
    Publication date: August 15, 2019
    Inventors: Henning Braunisch, Kemel Aygun, Ajay Jain, Zhiguo Qian