Abstract: A method and system for controlling an output signal power level of a wireless transmitter can be created by detecting the signal power level of the transmitter with a detector, selectively attenuating the output signal power level with an attenuator having variable attenuation levels, and monitoring the output signal power level and comparing the output signal power level, as determined by the detector, to a predetermined threshold with a processor. The processor preferably controls the attenuator in accordance with the comparison of the output signal power level and the predetermined threshold.

Abstract: A method and system for controlling an output signal power level of a wireless transmitter can be created by detecting the signal power level of the transmitter with a detector, selectively attenuating the output signal power level with an attenuator having variable attenuation levels, and monitoring the output signal power level and comparing the output signal power level, as determined by the detector, to a predetermined threshold with a processor. The processor preferably controls the attenuator in accordance with the comparison of the output signal power level and the predetermined threshold.

Abstract: A method and system for modulating data onto a carrier signal in a plurality of channels, each of the channels having a channel bandwidth, can be created for use in any two-way satellite communication system or other wireless communication application where frequency hopping with or without Doppler compensation is desired. The system preferably includes a digital modulator that outputs a modulated baseband signal, an intermediate frequency modulator that receives the modulated baseband signal and outputs an intermediate frequency signal derived from the modulated baseband signal, a frequency synthesizing system that outputs a synthesized intermediate frequency signal to the intermediate frequency modulator, and a circuit (numerically controlled oscillator) connected to the digital modulator which provides a signal to the digital modulator.

Abstract: A method and system for controlling an output signal power level of a wireless transmitter can be created by detecting the signal power level of the transmitter with a detector, selectively attenuating the output signal power level with an attenuator having variable attenuation levels, and monitoring the output signal power level and comparing the output signal power level, as determined by the detector, to a predetermined threshold with a processor. The processor preferably controls the attenuator in accordance with the comparison of the output signal power level and the predetermined threshold.

Abstract: A method and system for modulating data onto a carrier signal in a plurality of channels, each of the channels having a channel bandwidth, can be created for use in any two-way satellite communication system or other wireless communication application where frequency hopping with or without Doppler compensation is desired. The system preferably includes a digital modulator that outputs a modulated baseband signal, an intermediate frequency modulator that receives the modulated baseband signal and outputs an intermediate frequency signal derived from the modulated baseband signal, a frequency synthesizing system that outputs a synthesized intermediate frequency signal to the intermediate frequency modulator, and a circuit (numerically controlled oscillator) connected to the digital modulator which provides a signal to the digital modulator.

Abstract: A method and apparatus for automatically detecting the format of a high-definition television (HDTV) signal at a video encoder to allow proper encoding of the signal, including progressive and interlaced scan, and specific pixel and vertical line resolutions. The system is compatible with video standards such as the SMPTE and MPEG-2 standards. A video sample clock is determined by phase-locking clock pulses in a video signal to one of two or more available reference clocks. An SAV/EAV counter and pixel sample counter determine the horizontal resolution of the video, e.g., pixels per line. The system discriminates between 24 frames per second video and 30 frames per second video, and between a 720 line progressive scan signal and a 1080 line interlaced scan signal, for example. The system uses PLLs for each reference clock, where a lock range of the PLLs is narrow such that two PLLs will not lock at the same time for one input frequency.

Abstract: A frequency-agile, direct digital synthesis (DDS) modulator includes a double conversion architecture which provides an output signal having a good output spectrum with low spurious signals. The modulator is particularly suitable for providing a quadrature phase-shift keyed (QPSK) data signal. The modulator includes a direct digital synthesizer (DDS) for generating a data signal in response to a clock signal operating at an associated clock frequency. Two local oscillators are provided for respectively up-converting and then down-converting the DDS data signal to provide the output signal having the desired spectral characteristics. The first local oscillator operates at a first mixing frequency, while the second local oscillator is responsive to the clock signal for providing a second mixing signal at the clock frequency. This configuration eliminates the need for a phase lock loop for the second oscillator.