Abstract: A dynamic read/write memory array has a column decode and data input/output arrangement constructed to compensate for large capacitive loads in the I/O circuitry. In a first stage, a buffer is employed between sense amplifiers and segmented intermediate I/O lines. Each segment is a small fraction of the I/O load. First-level column decoding selects one column for each segment. A second level of column decoding employs tri-state buffers which can only be activated during a read with the proper column address. When writing, all buffers are in the high impedance state for reading while the selected buffer is written into through decoded pass gates.

Abstract: A semiconductor dynamic read/write memory device using one-transistor storage cells and balanced bit lines employs a differential sense amplifier having dual sets of transistors for both the N-channel and P-channel transistor pairs in a CMOS flip-flop circuit. One set of P and N channel transistors is cross-coupled in the conventional manner, and the other set is cross-coupled by way of series transistors which are shut off for write operations, bypassing static loads for write.