Abstract: This application provides a resonant conversion system, including a controller and a resonant conversion circuit. The resonant conversion circuit includes a high frequency chopper circuit, a resonant cavity, a transformer, and a rectification filter network, and the high frequency chopper circuit includes switches S1 and S2. The controller is configured to: detect a bridge arm midpoint voltage VSW, and determine based on the VSW a current threshold signal used to indicate a current threshold; detect a resonant current on a primary side of the transformer, and compare the resonant current with the current threshold signal to control on/off of the switch S1 or S2 based on the second electrical signal, so that the system operates in an inductive mode to ensure zero voltage switching of the switch, while operating in a state close to a capacitive mode to maximize the use of a gain region.

Abstract: A voltage conversion apparatus, a control method, and a power supply device. The voltage conversion apparatus includes a control circuit. The control circuit is configured to: obtain a first sampling voltage and a second sampling voltage; detect a resonant period based on the second sampling voltage when it is determined, based on the first sampling voltage, that a voltage range of an output voltage of the voltage conversion apparatus changes and a voltage threshold is exceeded; and output a drive signal based on the detected resonant period. The drive signal is used to control turn-on and turn-off of a first switching transistor and a second switching transistor.

Abstract: The control system includes a PFC circuit and a sampling control circuit, and the PFC circuit includes an inductor, a first power supply drive circuit, and a first bridge arm and a second bridge arm that are connected in parallel, and a first bridge arm midpoint is a serial connection point between a first upper bridge arm and a first lower bridge arm of the first bridge arm. The sampling control circuit is configured to control, based on voltages of two ends of an alternating current power supply, the first lower bridge arm to be turned on, so that the first power supply drive circuit starts charging. The sampling control circuit is further configured to: when charging duration of the first power supply drive circuit reaches first target duration, control the first lower bridge arm to be turned off, so that the first power supply drive circuit completes charging.

Abstract: This application describes a totem-pole power factor correction circuit and a power supply module. A detection circuit of the totem-pole power factor correction circuit can detect a current between a power transistor and a bridge arm middle point, and determine a current value when an inductor is charged. When a control circuit controls a drive circuit to drive the power transistor to be turned on, in response to a value of a current flowing through the inductor being greater than a first predetermined value, the drive circuit can drive, in time based on a detection result of the detection circuit, the power transistor to be turned off, to protect the power transistor.

Abstract: A power supply apparatus includes a totem-pole power factor correction (PFC) circuit and a control apparatus, and the totem-pole PFC circuit includes a first switching transistor and a second switching transistor. The control apparatus includes a controller and a dead time detection circuit, and the dead time detection circuit includes a detection capacitor and a detection resistor. A first end of the detection capacitor is connected to a first reference point, a second end of the detection capacitor is connected to a first end of the detection resistor, and a second end of the detection resistor is grounded. The controller is configured to, respectively, control an on/off status of the first switching transistor and an on/off status of the second switching transistor based on a voltage of the detection resistor and polarity of a voltage input by an alternating current input source.

Abstract: A power module, a totem-pole power factor correction circuit, and a control circuit thereof. In response to a case in which a phase value of a transient voltage of an input voltage of the totem-pole power factor correction circuit is within a predetermined phase range, and an absolute value of a voltage value is less than a predetermined voltage value, the control circuit controls a main power switch in the totem-pole power factor correction circuit to be turned on and off, and controls an auxiliary power switch to remain off.

Abstract: A power conversion circuit and a power conversion circuit control method. The power conversion circuit determines polarity of an alternating current voltage by using a PFC circuit controller, determines, based on a current of an inductor, a signal for controlling a secondary switch to be turned off, determines, based on a voltage at a midpoint of a series connection between a switching transistor S1 and a switching transistor S2, a signal for controlling the secondary switch to be turned on again and a signal for controlling a primary switch to be turned off, and performs PWM control on the switching transistor S1 and the switching transistor S2.

Abstract: A method for controlling a totem-pole PFC circuit. When an alternating current of an input end of a totem-pole PFC circuit is in a positive half period, if a previous switching period is less than specified duration, after charging of a PFC inductor is completed, a switch that enables the PFC inductor to be discharged is first delayed for specified threshold duration, and then the switch that enables the PFC inductor to be discharged is turned on, so that the switch that enables the PFC inductor to be discharged is turned on only once. In an existing PFC application, when an input voltage is in a positive half period, a switch that enables a PFC inductor to be discharged needs to be turned on twice.

Abstract: A noise suppression method and apparatus for a totem pole power factor correction (PFC) circuit and an electronic device are provided. In response to a determination that an alternating current of the totem pole PFC circuit is switched at a zero crossing, a control signal is sent to a switch that enables a PFC inductor in the totem pole PFC circuit to charge or discharge. After the switch is turned off for a first period of time, the switch is turned on again for a second period of time.

Abstract: An example of a totem-pole bridgeless power factor correction circuit includes a first drive circuit, a rectifier bridge, an inductor, and a current detection circuit. The rectifier bridge includes a first metal oxide semiconductor (MOS) transistor and a first resistor that are located in a first bridge arm. The first drive circuit is configured to drive, based on a first PWM signal when a voltage of a second output port of an alternating current power supply is a positive voltage, a first port and a second port of the first MOS transistor to turn on the first MOS transistor to enable the alternating current power supply to charge the inductor by using the first MOS transistor.

Abstract: A power factor correction (PFC) circuit includes an alternating current input circuit, a totem-pole PFC circuit, an input sampling circuit, an output sampling circuit, and a PFC control protection circuit. A first output terminal of the alternating current input circuit is respectively connected to a first input terminal of the totem-pole PFC circuit and a first input terminal of the input sampling circuit.

Abstract: A high power factor rectifier circuit includes a totem pole power factor correction (PFC) circuit, a sampling resistor, a power suppl a PFC controller, and a filter. The totem pole PFC circuit includes two bridge arm units connected in parallel between a first parallel connection point and a second parallel connection point. One end of the sampling resistor is connected to the first parallel connection point and a first reference ground, and the other end of the sampling resistor is separately connected to a sampling voltage input terminal of the PFC controller and a second reference ground. A grounding terminal of the PFC controller is connected to the first reference ground. A power output terminal of the power supply is connected to a power input terminal of the PFC controller using the filter.

Abstract: A pin state configuration circuit, a method for configuring pin states and an electronic device for configuring pin states are provided. The pin state configuration circuit includes a configured resistor load, a voltage sampling unit, and a comparator. The voltage sampling unit supplies a reference voltage to the configured resistor load by using a first or second configuration pin, and respectively samples voltages of the first and second configuration pins. The comparator calculates a first voltage ratio based on the voltage of the first configuration pin and the voltage of the second configuration pin, calculates a second voltage ratio based on the voltage of the first configuration pin and the voltage of the second configuration pin, and determines a corresponding pin configuration state based on the first and second voltage ratios. In this way, N×N pin configuration states may be obtained by configuring two configuration pins.

Abstract: This application provides a resonant conversion system, including a controller and a resonant conversion circuit. The resonant conversion circuit includes a high frequency chopper circuit, a resonant cavity, a transformer, and a rectification filter network, and the high frequency chopper circuit includes switches S1 and S2. The controller is configured to: detect a bridge arm midpoint voltage VSW, and determine based on the VSW a current threshold signal used to indicate a current threshold; detect a resonant current on a primary side of the transformer, and compare the resonant current with the current threshold signal to control on/off of the switch S1 or S2 based on the second electrical signal, so that the system operates in an inductive mode to ensure zero voltage switching of the switch, while operating in a state close to a capacitive mode to maximize the use of a gain region.

Abstract: A pin state configuration circuit, a method for configuring pin states and an electronic device for configuring pin states are provided. The pin state configuration circuit includes a configured resistor load, a voltage sampling unit, and a comparator. The voltage sampling unit supplies a reference voltage to the configured resistor load by using a first or second configuration pin, and respectively samples voltages of the first and second configuration pins. The comparator calculates a first voltage ratio based on the voltage of the first configuration pin and the voltage of the second configuration pin, calculates a second voltage ratio based on the voltage of the first configuration pin and the voltage of the second configuration pin, and determines a corresponding pin configuration state based on the first and second voltage ratios. In this way, N×N pin configuration states may be obtained by configuring two configuration pins.

Abstract: The control system includes a PFC circuit and a sampling control circuit, and the PFC circuit includes an inductor, a first power supply drive circuit, and a first bridge arm and a second bridge arm that are connected in parallel, and a first bridge arm midpoint is a serial connection point between a first upper bridge arm and a first lower bridge arm of the first bridge arm. The sampling control circuit is configured to control, based on voltages of two ends of an alternating current power supply, the first lower bridge arm to be turned on, so that the first power supply drive circuit starts charging. The sampling control circuit is further configured to: when charging duration of the first power supply drive circuit reaches first target duration, control the first lower bridge arm to be turned off, so that the first power supply drive circuit completes charging.

Abstract: A method for scheduling a network resource comprises adding tokens to first and second accumulators at first and second fill rates, respectively. A number of tokens corresponding to a size of a packet is subtracted from the first accumulator and a highest priority is assigned to a queue with which the packet is associated, if a number of tokens in the first accumulator is greater than zero. The number of tokens is subtracted from the second accumulator, and a default priority assigned to the queue, if the number of tokens in the first accumulator is less than zero and a number of tokens in the second accumulator is greater than zero. The network resource is assigned for transmission of the packet from the queue using a schedule that is based on the priority assigned to the queue. The packet is transmitted using the assigned network resource.

Abstract: A method for scheduling a network resource comprises adding tokens to first and second accumulators at first and second fill rates, respectively. A number of tokens corresponding to a size of a packet is subtracted from the first accumulator and a highest priority is assigned to a queue with which the packet is associated, if a number of tokens in the first accumulator is greater than zero. The number of tokens is subtracted from the second accumulator, and a default priority assigned to the queue, if the number of tokens in the first accumulator is less than zero and a number of tokens in the second accumulator is greater than zero. The network resource is assigned for transmission of the packet from the queue using a schedule that is based on the priority assigned to the queue. The packet is transmitted using the assigned network resource.

Abstract: The present invention is a diaphragm-fiber optic sensor (DFOS), interferometric sensor. This DFOS is based on the principles of Fabry-Perot and Michelson/Mach-Zehnder. The sensor is low cost and is designed with high efficiency, reliability, and Q-point stability, fabricated using MEMS (micro mechanic-electrical system) technology, and has demonstrated excellent performance. A DFOS according to the invention includes a cavity between two surfaces: a diaphragm made of silicon or other material with a rigid body (or boss) at the center and clamped along its edge, and the endface of a single mode optic fiber. By utilizing MEMS technology, the gap width between the diaphragm and the fiber endface is made accurately, ranging from 1 micron to 10 microns.

Abstract: The theory, design, fabrication, and characterization of MEMS (micro electrical mechanical system) Fabry-Perot diaphragm-fiber optic microphone are described in the present invention. By using MEMS technology in processing and packaging, a square 1.9 mm×1.9 mm, 2? thick SiO2 diaphragm with a 350? square embossed center of silicon is mechanically clamped to the ferrule of a single mode fiber to keep its closeness (5?) and perpendicular orientation with respect to the diaphragm. Static measurement of optical output power versus the pressure on membrane reveals more than one period of Fabry-Perot interference, thereby generating a Fabry-Perot diaphragm-fiber interferometer device accurately reproducing audible acoustic wave.