Abstract: A method for testing an integrated circuit for potential latchup sites includes applying a voltage to the integrated circuit, measuring a current through the integrated circuit, applying at least one radiation beam to at least one area of the integrated circuit, and detecting an occurrence of a latchup by detecting an increase of the current through the integrated circuit upon applying the at least one radiation beam to the at least one area of the integrated circuit.

Abstract: A method for testing an integrated circuit for potential latchup sites includes applying a voltage to the integrated circuit, measuring a current through the integrated circuit, applying at least one radiation beam to at least one area of the integrated circuit, and detecting an occurrence of a latchup by detecting an increase of the current through the integrated circuit upon applying the at least one radiation beam to the at least one area of the integrated circuit.

Abstract: A semiconductor substrate having a surface, a field oxide region at the surface and a gate structure above the surface are provided. A sidewall spacer is formed adjacent to the gate structure and a polysilicon layer is formed above the substrate, the polysilicon layer having raised first and second portions above the gate structure and field oxide region, respectively. A masking layer is formed above the polysilicon layer and then blanket etched to expose the raised first and second portions of the polysilicon layer which are subsequently removed to form a raised source/drain region from the polysilicon layer. Since the raised source/drain region is fabricated without using photolithography, high density MOSFETs are readily fabricated.

Abstract: A semiconductor substrate having a surface, a planarized field oxide region at the surface and a gate structure overlying the surface are provided. A sidewall spacer is formed adjacent to the gate structure and a polysilicon layer is formed overlying the substrate, the polysilicon layer having a raised first portion overlying the gate structure. A masking layer is formed overlying the polysilicon layer and then blanket etched to expose the raised first portion of the polysilicon layer which is subsequently removed. Since the raised first portion of the polysilicon layer is removed without using photolithography, high density MOSFETs are readily fabricated.