Patents by Inventor Ken Creta

Ken Creta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • General input/output architecture, protocol and related methods to manage data integrity
    Patent number: 7353313
    Abstract: An enhanced general input/output (EGIO) communication architecture, protocol and related methods are presented. The elements of an EGIO architecture may include one or more of a root complex (e.g., implemented within a bridge), a switch, and end-points, each incorporating at least a subset of EGIO features to support EGIO communication between such elements.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: April 1, 2008
    Assignee: Intel Corporation
    Inventors: Eric R. Wehage, Jasmin Ajanovic, David Harriman, David M. Lee, Blaise Fanning, Buck Gremel, Ken Creta, Wayne Moore
  • General input/output architecture, protocol and related methods to manage data integrity
    Publication number: 20070038793
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Application
    Filed: October 23, 2006
    Publication date: February 15, 2007
    Inventors: Eric Wehage, Jasmin Ajanovic, David Harriman, David Lee, Blaise Fanning, Buck Gremel, Ken Creta, Wayne Moore
  • General input/output architecture, protocol and related methods to manage data integrity
    Patent number: 7152128
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method is described comprising receiving a datagram at general input/output (GIO) interface from a remote GIO interface coupled through a GIO link, validating content of one or more packets embedded within the received datagram, and issuing an acknowledgment to the remote GIO interface that the datagram was successfully received on positive validation of the datagram before promoting the embedded packets to a transaction layer of the GIO interface. Other embodiments are also described.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: December 19, 2006
    Assignee: Intel Corporation
    Inventors: Eric R. Wehage, Jasmin Ajanovic, David Harriman, David M. Lee, Blaise Fanning, Buck Gremel, Ken Creta, Wayne Moore
  • Method and apparatus for invalidating a cache line without data return in a multi-node architecture
    Patent number: 6772298
    Abstract: A method of invalidating a cache line in a system having a plurality of nodes that include a processor and a cache memory. A request to invalidate a cache line that is caching a particular memory block is sent from a first node. The request is a request to invalidate a cache line in another node without returning to the first node the data stored in a cache line to be invalidated. In an embodiment, the data in the cache line to be invalidated is not returned to the first node even if the cache line is in the modified state. In a further embodiment, new data is written to a cache line in the first node that is caching the particular memory block without writing old data that was stored in that cache line back to a memory.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: August 3, 2004
    Assignee: Intel Corporation
    Inventors: Manoj Khare, Akhilesh Kumar, Ken Creta, Lily P. Looi, Robert T. George, Michel Cekleov
  • General input/output architecture, protocol and related methods to manage data integrity
    Publication number: 20030145134
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Application
    Filed: August 23, 2002
    Publication date: July 31, 2003
    Inventors: Eric R. Wehage, Jasmin Ajanovic, David Harriman, David M. Lee, Blaise Fanning, Buck Gremel, Ken Creta, Wayne Moore
  • Method and apparatus for invalidating a cache line without data return in a multi-node architecture
    Publication number: 20020078305
    Abstract: A method of invalidating cache a line in a system having a plurality of nodes that include a processor and a cache memory. A request to invalidate a cache line that is caching a particular memory block is sent from a first node. The request is a request to invalidate a cache line in another nodes without returning to the first node the data stored in a cache line to be invalidated. In an embodiment, the data in the cache line to be invalidated is not returned to the first node even if the cache line is in the modified state. In a further embodiment, new data is written to a cache line in the first node that is caching the particular memory block without writing old data that was stored in that cache line back to a memory.
    Type: Application
    Filed: December 20, 2000
    Publication date: June 20, 2002
    Inventors: Manoj Khare, Akhilesh Kumar, Ken Creta, Lily P. Looi, Robert T. George, Michel Cekleov