Patents by Inventor Ken Henmi
Ken Henmi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7452744Abstract: A first gate electrode and a second gate electrode are formed on a semiconductor substrate, and then a resist pattern is formed so as to selectively leave open a portion including an overlap between the first and second gate electrodes. Next, the overlap between the gate electrodes is removed through isotropic etching. Etching is carried out at this time by an amount within a range of 140% to 200% of the film thickness of the second gate electrode. Next, a normal inter-layer insulating film and light-shielding film are formed. It is possible to eliminate the overlap between the gate electrodes adjacent to an opening of the light-shielding film, suppress the height of the light-shielding film at that portion, reduce shading for the light condensed by a lens and thereby improve the light condensing efficiency of the lens.Type: GrantFiled: December 14, 2005Date of Patent: November 18, 2008Assignee: Panasonic CorporationInventors: Ken Henmi, Toshihiro Kuriyama
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Patent number: 7098066Abstract: A charge coupled device of the present invention includes a charge transfer region layer and a gate insulation film that are formed in the stated order on a semiconductor substrate, first gate electrodes formed at predetermined spaces on the gate insulation film, and second gate electrodes arranged between the first gate electrodes with at least silicon oxide films being interposed there between. Each silicon oxide film has constricted portions where the silicon oxide film is in contact with the gate insulation film, and electric insulation films are formed on the constricted portions so as to form sidewalls. This configuration decreases the charge transfer efficiency and increases a dielectric breakdown voltage between gate electrodes. Thus, a charge coupled device having high performance and high dielectric strength is provided.Type: GrantFiled: April 23, 2004Date of Patent: August 29, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Tanaka, Ken Henmi
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Publication number: 20060134807Abstract: A first gate electrode and a second gate electrode are formed on a semiconductor substrate, and then a resist pattern is formed so as to selectively leave open a portion including an overlap between the first and second gate electrodes. Next, the overlap between the gate electrodes is removed through isotropic etching. Etching is carried out at this time by an amount within a range of 140% to 200% of the film thickness of the second gate electrode. Next, a normal inter-layer insulating film and light-shielding film are formed. It is possible to eliminate the overlap between the gate electrodes adjacent to an opening of the light-shielding film, suppress the height of the light-shielding film at that portion, reduce shading for the light condensed by a lens and thereby improve the light condensing efficiency of the lens.Type: ApplicationFiled: December 14, 2005Publication date: June 22, 2006Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Ken Henmi, Toshihiro Kuriyama
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Publication number: 20050196946Abstract: A first impurity region 2 of a reverse conductivity type configuring a photoelectric conversion element and a buried channel region 3 of a reverse conductivity type configuring an element for transferring signal charges are formed in a principal surface portion of a semiconductor substrate 1 of one conductivity type, and a first insulating film 4 is formed on the semiconductor substrate. Then, a readout electrode 5 is formed in an area including a region on the buried channel region, and a second insulating film 6 for covering the readout electrode is formed. After that, a side wall forming film 7a is formed and a selective etching is carried out based on an etching selectivity ratio, thereby forming side walls 7 on side faces of the readout electrode with the second insulating film interposed therebetween.Type: ApplicationFiled: March 1, 2005Publication date: September 8, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Ken Henmi
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Publication number: 20040203182Abstract: A charge coupled device of the present invention includes a charge transfer region layer and a gate insulation film that are formed in the stated order on a semiconductor substrate, first gate electrodes formed at predetermined spaces on the gate insulation film, and second gate electrodes arranged between the first gate electrodes with at least silicon oxide films being interposed therebetween. Each silicon oxide film has constricted portions where the silicon oxide film is in contact with the gate insulation film, and electric insulation films are formed on the constricted portions so as to form sidewalls. This configuration decreases the charge transfer efficiency and increases a dielectric breakdown voltage between gate electrodes. Thus, a charge coupled device having high performance and high dielectric strength is provided.Type: ApplicationFiled: April 23, 2004Publication date: October 14, 2004Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Tanaka, Ken Henmi
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Patent number: 6750510Abstract: A charge coupled device of the present invention includes a charge transfer region layer and a gate insulation film that are formed in the stated order on a semiconductor substrate, first gate electrodes formed at predetermined spaces on the gate insulation film, and second gate electrodes arranged between the first gate electrodes with at least silicon oxide films being interposed therebetween. Each silicon oxide film has constricted portions where the silicon oxide film is in contact with the gate insulation film, and electric insulation films are formed on the constricted portions so as to form sidewalls. This configuration increases the charge transfer efficiency and increases a dielectric breakdown voltage between gate electrodes. Thus a charge coupled device having high performance and high dielectric strength is provided.Type: GrantFiled: January 29, 2003Date of Patent: June 15, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Tanaka, Ken Henmi
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Publication number: 20030146471Abstract: A charge coupled device of the present invention includes a charge transfer region layer and a gate insulation film that are formed in the stated order on a semiconductor substrate, first gate electrodes formed at predetermined spaces on the gate insulation film, and second gate electrodes arranged between the first gate electrodes with at least silicon oxide films being interposed therebetween. Each silicon oxide film has constricted portions where the silicon oxide film is in contact with the gate insulation film, and electric insulation films are formed on the constricted portions so as to form sidewalls. This configuration decreases the charge transfer efficiency and increases a dielectric breakdown voltage between gate electrodes. Thus, a charge coupled device having high performance and high dielectric strength is provided.Type: ApplicationFiled: January 29, 2003Publication date: August 7, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Tanaka, Ken Henmi