Patents by Inventor Ken Hirashima

Ken Hirashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • External memory control techniques with multiprocessors improving the throughput of data between a hierarchically upper processing unit and an external memory with efficient use of a cache memory
    Patent number: 5335327
    Abstract: A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU, the cache memory holding temporarily copies of the information stored in the DKU. A request from the CPU for access to the information stored in the DKU is met as far as possible by use of the information held in the cache memory. First transfer routes of information between the CPU and the cache memory is greater in number than second transfer routes of information between the cache memory and the DKU. This makes it possible that even when direct accesses to the DKU in the same number as the second transfer routes occur in each of the first transfer route, accesses to the cache memory which may arise from other CPUs are capable of being effected through the remaining ones of the first transfer routes.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: August 2, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoshi Hisano, Ken Hirashima, Hiroyuki Kurosawa, Kenji Kubota, Shuji Sugimoto
  • Disk unit with processors which detect cache status and control port selection for optimizing utilization of cache interfacing host and external memory
    Patent number: 5241640
    Abstract: A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU, the cache memory holding temporarily copies of the information stored in the DKU. A request from the CPU for access to the information stored in the DKU is met as far as possible by use of the information held in the cache memory. First transfer routes of information between the CPU and the cache memory is greater in number than second transfer routes of information between the cache memory and the DKU. This makes it possible that even when direct accesses to the DKU in the same number as the second transfer routes occur in each of the first transfer route, acesses to the cache memory which may arise from other CPUs are capable of being effected through the remaining ones of the first transfer routes.
    Type: Grant
    Filed: October 10, 1989
    Date of Patent: August 31, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoshi Hisano, Ken Hirashima, Hiroyuki Kurosawa, Kenji Kubota, Shuji Sugimoto