Abstract: Integrated circuits with amplification circuitry are provided. The amplification circuitry may have an input terminal, an output terminal, a positive power supply terminal, and a ground terminal. The amplification circuitry may include first, second, and third stages. The first stage may provide biasing for the second stage. The second stage may provide biasing for the third stage. The second stage may provide paths for conveying an input signal from the input terminal to the third stage. The second stage may bias the amplifier to have low quiescent current and low shoot-through current. The second stage may prevent PVT variations such as supply voltage variations from affecting the quiescent current and shoot-through current of the amplifier. To increase the high-frequency response of the amplifier, capacitors may be added to the paths for conveying the input signal from the input terminal to the third stage.

Abstract: Integrated circuits with amplification circuitry are provided. The amplification circuitry may have an input terminal, an output terminal, a positive power supply terminal, and a ground terminal. The amplification circuitry may include first, second, and third stages. The first stage may provide biasing for the second stage. The second stage may provide biasing for the third stage. The second stage may provide paths for conveying an input signal from the input terminal to the third stage. The second stage may bias the amplifier to have low quiescent current and low shoot-through current. The second stage may prevent PVT variations such as supply voltage variations from affecting the quiescent current and shoot-through current of the amplifier. To increase the high-frequency response of the amplifier, capacitors may be added to the paths for conveying the input signal from the input terminal to the third stage.

Abstract: A data processing system including a database, a file server coupled to the database, a template engine coupled to the file server. The template engine being configured to create a plurality of insurance brokerage industry templates. The system further including an application service provider interface logic coupled to the file server and the template engine. The application service provider interface logic being configured to receive commands via a communication network from a client device to access an open platform template library in the database and retrieve one of the plurality of insurance brokerage industry templates.

Abstract: A data processing system including a database, a file server coupled to the database, a template engine coupled to the file server. The template engine being configured to create a plurality of insurance brokerage industry templates. The system further including an application service provider interface logic coupled to the file server and the template engine. The application service provider interface logic being configured to receive commands via a communication network from a client device to access an open platform template library in the database and retrieve one of the plurality of insurance brokerage industry templates.

Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.

Abstract: An input-output (I/O) buffer and a method of biasing an I/O buffer that avoids inadvertent conduction of a pull-up transistor included in the buffer when an input signal having a voltage greater than the supply voltage is applied to the I/O buffer in an input mode. Inadvertent conduction of the pull-up transistor is avoided during an input mode by biasing the gate and the body of the pull-up transistor with a supply voltage until the voltage of the input signal exceeds the voltage of the voltage supply, at which time the voltage of the input signal is applied to the gate and the body of the pull-up transistor instead. The I/O buffer includes a driver circuit having a pull-up transistor and an I/O node to receive an input signal. The I/O buffer also includes a pull-up transistor bias circuit to provide the voltage to the gate and the body of the pull-up transistor.

Abstract: An input-output (I/O) buffer and a method of biasing an I/O buffer that avoids inadvertent conduction of a pull-up transistor included in the buffer when an input signal having a voltage greater than the supply voltage is applied to the I/O buffer in an input mode. Inadvertent conduction of the pull-up transistor is avoided during an input mode by biasing the gate and the body of the pull-up transistor with a supply voltage until the voltage of the input signal exceeds the voltage of the voltage supply, at which time the voltage of the input signal is applied to the gate and the body of the pull-up transistor instead. The I/O buffer includes a driver circuit having a pull-up transistor and an I/O node to receive an input signal. The I/O buffer also includes a pull-up transistor bias circuit to provide the voltage to the gate and the body of the pull-up transistor.