Patents by Inventor Ken-ichi Ichino

Ken-ichi Ichino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for determining optimum initial value for test pattern generator
    Patent number: 7299394
    Abstract: The purpose of the invention is to determine an optimum initial value to be input to a test pattern generator in order to achieve efficient testing of an integrated circuit. To achieve this purpose, a minimum test length is obtained by performing a fault simulation and a reverse-order fault simulation using an arbitrarily given initial value; the next initial value that is likely to yield a test length shorter than the minimum test length is computed and a fault simulation is performed using the thus computed initial value; and the next initial value that is likely to yield a test length shorter than that test length is computed and a fault simulation is performed using the thus computed initial value. By repeating this process, an initial value that yields the shortest test length is obtained.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: November 20, 2007
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Ken-ichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Takeshi Shoda, Masayuki Sato
  • Method and apparatus for determining optimum initial value for test pattern generator
    Publication number: 20040088626
    Abstract: The purpose of the invention is to determine an optimum initial value to be input to a test pattern generator in order to achieve efficient testing of an integrated circuit. To achieve this purpose, a minimum test length is obtained by performing a fault simulation and a reverse-order fault simulation using an arbitrarily given initial value; the next initial value that is likely to yield a test length shorter than the minimum test length is computed and a fault simulation is performed using the thus computed initial value; and the next initial value that is likely to yield a test length shorter than that test length is computed and a fault simulation is performed using the thus computed initial value. By repeating this process, an initial value that yields the shortest test length is obtained.
    Type: Application
    Filed: March 28, 2003
    Publication date: May 6, 2004
    Applicant: Semiconductor Tchnology Academic Research Center
    Inventors: Ken-ichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Takeshi Shoda, Masayuki Sato