Patents by Inventor Ken Idota

Ken Idota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100283084
    Abstract: The bipolar transistor includes a heterojunction intrinsic base layer epitaxially grown on a collector layer. The intrinsic base layer is disposed on the collector layer surrounded by an isolation layer, and an N-type impurity layer is formed in a surface portion of the collector layer. The impurity concentration of the N-type impurity layer is higher than the impurity concentration of the collector layer under the N-type impurity layer. Between the N-type impurity layer and the intrinsic base layer, an epitaxially grown layer is formed, where the epitaxially grown layer is lower in impurity concentration than the N-type impurity layer and the intrinsic base layer.
    Type: Application
    Filed: March 24, 2010
    Publication date: November 11, 2010
    Inventors: Teruhito Ohnishi, Ken Idota, Atsushi Nakamura
  • Patent number: 7719031
    Abstract: A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: May 18, 2010
    Assignee: Panasonic Corporation
    Inventors: Tohru Saitoh, Takahiro Kawashima, Ken Idota, Yoshihiko Kanzawa, Teruhito Ohnishi
  • Patent number: 7465969
    Abstract: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: December 16, 2008
    Assignee: Panasonic Corporation
    Inventors: Teruhito Ohnishi, Koichiro Yuki, Tsuneichiro Sano, Tohru Saitoh, Ken Idota, Takahiro Kawashima, Shigeki Sawada
  • Publication number: 20070085167
    Abstract: A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.
    Type: Application
    Filed: July 6, 2004
    Publication date: April 19, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tohru Saitoh, Takahiro Kawashima, Ken Idota, Yoshihiko Kanzawa, Teruhito Ohnishi
  • Publication number: 20060226446
    Abstract: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.
    Type: Application
    Filed: June 12, 2006
    Publication date: October 12, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Teruhito Ohnishi, Koichiro Yuki, Tsuneichiro Sano, Tohru Saitoh, Ken Idota, Takahiro Kawashima, Shigeki Sawada
  • Patent number: 7091099
    Abstract: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: August 15, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Teruhito Ohnishi, Koichiro Yuki, Tsuneichiro Sano, Tohru Saitoh, Ken Idota, Takahiro Kawashima, Shigeki Sawada
  • Patent number: 6987072
    Abstract: A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: January 17, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiko Kanzawa, Teruhito Ohnishi, Ken Idota, Tohru Saitoh, Akira Asai
  • Patent number: 6927118
    Abstract: The present invention discloses a process of fabricating a semiconductor device comprising the steps of: forming a collector layer of a first conductivity type at a portion of a surface of a semiconductor substrate; forming a collector opening portion in a first insulating layer formed on the semiconductor substrate; epitaxially growing, on the semiconductor substrate of the collector opening portion, a semiconductor layer including a layer of a second conductivity type constituting a base layer; sequentially layering, on the semiconductor substrate, an etching stopper layer against dry etching and a masking layer against wet etching; exposing a part of the etching stopper layer by removing a part of the masking layer by means of dry etching; and by subjecting the exposed etching stopper layer to a wet etching treatment using the remaining masking layer as a mask, forming a base junction opening portion through the etching stopper layer and the masking layer.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: August 9, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ken Idota, Teruhito Ohnishi, Akira Asai
  • Publication number: 20050092230
    Abstract: A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.
    Type: Application
    Filed: December 13, 2004
    Publication date: May 5, 2005
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yoshihiko Kanzawa, Teruhito Ohnishi, Ken Idota, Tohru Saitoh, Akira Asai
  • Patent number: 6838395
    Abstract: A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: January 4, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiko Kanzawa, Teruhito Ohnishi, Ken Idota, Tohru Saitoh, Akira Asai
  • Publication number: 20040195655
    Abstract: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.
    Type: Application
    Filed: March 24, 2004
    Publication date: October 7, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Teruhito Ohnishi, Koichiro Yuki, Tsuneichiro Sano, Tohru Saitoh, Ken Idota, Takahiro Kawashima, Shigeki Sawada
  • Publication number: 20040092076
    Abstract: The present invention discloses a process of fabricating a semiconductor device comprising the steps of: forming a collector layer of a first conductivity type at a portion of a surface of a semiconductor substrate; forming a collector opening portion in a first insulating layer formed on the semiconductor substrate; epitaxially growing, on the semiconductor substrate of the collector opening portion, a semiconductor layer including a layer of a second conductivity type constituting a base layer; sequentially layering, on the semiconductor substrate, an etching stopper layer against dry etching and a masking layer against wet etching; exposing a part of the etching stopper layer by removing a part of the masking layer by means of dry etching; and by subjecting the exposed etching stopper layer to a wet etching treatment using the remaining masking layer as a mask, forming a base junction opening portion through the etching stopper layer and the masking layer.
    Type: Application
    Filed: October 29, 2003
    Publication date: May 13, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd
    Inventors: Ken Idota, Teruhito Ohnishi, Akira Asai
  • Patent number: 6273959
    Abstract: There is disclosed a semiconductor device cleaning method involving placing a cleaning solution containing 24 wt. % sulfuric acid, 5 wt. % hydrogen peroxide, 0.02 wt. % hydrogen fluoride, 0.075 wt. % n-dodecylbenzenesulfonic acid, and water into a quartz processing vessel and heating to no more than 100° C. A silicon wafer is immersed into the cleaning solution for 10 minutes and then washed by demineralized water for about 7 minutes. The surfaces of foreign particles on the wafer are etched by hydrogen fluoride, and n-dodecylbenzenesulfonic acid combines with the etched surfaces by sulfate ester bonding. The apparent diameter of the foreign particles increases and the repulsive force caused by zeta potential etc. increases, so that the foreign particles are unlikely to adhere to the surface of the silicon wafer permitting the foreign particles to be easily washed away in a water cleaning step.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: August 14, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Teruhito Oonishi, Ken Idota, Masaaki Niwa, Yoshinao Harada
  • Patent number: 5194400
    Abstract: A method for fabricating an AlGaInP-based visible light laser device by molecular beam epitaxy is described. In this method, a upper clad layer of (Al.sub.x Ga.sub.1-x).sub.y In.sub.1-y P wherein x and y are, respectively, in the ranges of from 0.5 to 1 and from 0.47 to 0.53 is covered with a protective layer serving also as an etching prevenive layer so that a grooved-type structure using the (Al.sub.x Ga.sub.1-x).sub.y In.sub.1-y P clad layer can be fabricated without involving degradation of the clad layer by contamination with oxygen, nitrogen and the like.
    Type: Grant
    Filed: November 29, 1991
    Date of Patent: March 16, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Takamori, Ken Idota, Kiyoshi Uchiyama, Masato Nakajima
  • Patent number: 5101449
    Abstract: An optical phase modulator for use with a fiber optic sensor such as a fiber optic gyroscope includes a piezoelectric vibrator which is asymmetric in at least one cross-sectional shape thereof, a pair of electrodes for applying a voltage to said piezoelectric vibrator, and an optical fiber joined to at least a portion of said piezoelectric vibrator by adhesive bonding. The piezoelectric vibrator has a cavity defined therein, and one of said electrodes is disposed on a surface of said piezoelectric vibrator which defines said axial cavity, the other electrode being disposed on an outer surface of said piezoelectric vibrator. The piezoelectric vibrator may be cylindrical, elliptically cylindrical, or planar in shape. The cavity may be cylindrical or elliptically cylindrical in shape.
    Type: Grant
    Filed: June 4, 1991
    Date of Patent: March 31, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshinori Takeuchi, Hidehiko Negishi, Yuko Takei, Ken Idota