Patents by Inventor Ken Jian Ming
Ken Jian Ming has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10051733Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.Type: GrantFiled: April 13, 2015Date of Patent: August 14, 2018Assignee: SanDisk Technologies Inc.Inventors: Chih-Chin Liao, Han-Shiao Chen, Chin-Tien Chiu, Ken Jian Ming Wang, Cheeman Yu, Hem Takiar
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Patent number: 9230919Abstract: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.Type: GrantFiled: October 30, 2014Date of Patent: January 5, 2016Assignee: SanDisk Technologies Inc.Inventors: Chin-Tien Chiu, Chih-Chin Liao, Ken Jian Ming Wang, Han-Shiao Chen, Cheeman Yu, Hem Takiar
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Patent number: 9209159Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.Type: GrantFiled: March 2, 2012Date of Patent: December 8, 2015Assignee: SanDisk Technologies Inc.Inventors: Hem Takiar, Cheeman Yu, Ken Jian Ming Wang, Chin-Tien Chiu, Han-Shiao Chen, Chih-Chin Liao
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Publication number: 20150223335Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.Type: ApplicationFiled: April 13, 2015Publication date: August 6, 2015Applicant: SANDISK TECHNOLOGIES INC.Inventors: Chih-Chin Liao, Han-Shiao Chen, Chin-Tien Chiu, Ken Jian Ming Wang, Cheeman Yu, Hem Takiar
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Patent number: 9006912Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.Type: GrantFiled: July 9, 2012Date of Patent: April 14, 2015Assignee: SanDisk Technologies Inc.Inventors: Chih-Chin Liao, Han-Shiao Chen, Chin-Tien Chiu, Ken Jian Ming Wang, Cheemen Yu, Hem Takiar
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Publication number: 20150054177Abstract: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.Type: ApplicationFiled: October 30, 2014Publication date: February 26, 2015Applicant: SANDISK TECHNOLOGIES INC.Inventors: Chin-Tien Chiu, Chih-Chin Liao, Ken Jian Ming Wang, Han-Shiao Chen, Cheeman Yu, Hem Takiar
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Patent number: 8878368Abstract: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.Type: GrantFiled: July 15, 2013Date of Patent: November 4, 2014Assignee: SanDisk Technologies Inc.Inventors: Chin-Tien Chiu, Chih-Chin Liao, Ken Jian Ming Wang, Han-Shiao Chen, Cheeman Yu, Hem Takiar
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Publication number: 20130299959Abstract: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.Type: ApplicationFiled: July 15, 2013Publication date: November 14, 2013Inventors: Chin-Tien Chiu, Chih-Chin Liao, Ken Jian Ming Wang, Han-Shiao Chen, Cheeman Yu, Hem Takiar
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Patent number: 8487441Abstract: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.Type: GrantFiled: October 31, 2007Date of Patent: July 16, 2013Assignee: SanDisk Technologies Inc.Inventors: Chin-Tien Chiu, Chih-Chin Liao, Ken Jian Ming Wang, Han-Shiao Chen, Cheemen Yu, Hem Takiar
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Patent number: 8461675Abstract: A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.Type: GrantFiled: December 13, 2005Date of Patent: June 11, 2013Assignee: SanDisk Technologies Inc.Inventors: Hem Takiar, Ken Jian Ming Wang, Chih-Chin Liao, Han-Shiao Chen
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Publication number: 20120273968Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.Type: ApplicationFiled: July 9, 2012Publication date: November 1, 2012Inventors: Chih-Chin Liao, Han-Shiao Chen, Chin-Tien Chiu, Ken Jian Ming Wang, Cheemen Yu, Hem Takiar
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Patent number: 8269323Abstract: Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner. A second integrated circuit package may be mounted to the first package.Type: GrantFiled: September 11, 2009Date of Patent: September 18, 2012Assignee: Broadcom CorporationInventors: Rezaur Rahman Khan, Ken Jian Ming Wang
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Patent number: 8269321Abstract: According to one exemplary embodiment, a lead frame package includes a number of leads and a number of contacts, where each of the contacts is situated over one of the leads. The lead frame package further includes a semiconductor die including a number of bond pads. Each of the contacts is directly attached and bonded to one of the bond pads on the semiconductor die. Each of the contacts is situated over a top portion of one of the leads, where the top portion has a shorter length than a middle portion of each of the leads. Each of the contacts is connected to one of the bond pads on the semiconductor die without a wire bond. The semiconductor die does not include a redistribution layer situated over an active surface of the semiconductor die.Type: GrantFiled: August 28, 2007Date of Patent: September 18, 2012Assignee: Broadcom CorporationInventors: Ken Jian Ming Wang, Matthew Vernon Kaufmann
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Publication number: 20120187545Abstract: Methods, systems, and apparatuses are described for improved integrated circuit packages. An integrated circuit package includes a semiconductor substrate and a semiconductor die. The semiconductor substrate has opposing first and second surfaces, a plurality of vias through the semiconductor substrate, and routing one or both surfaces of the semiconductor substrate. The die is mounted to the first surface of the semiconductor substrate. An encapsulating material encapsulates the die on the first surface of the semiconductor substrate.Type: ApplicationFiled: June 30, 2011Publication date: July 26, 2012Applicant: BROADCOM CORPORATIONInventors: Rezaur Rahman Khan, Edward Law, Ken Jian Ming Wang
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Patent number: 8217522Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.Type: GrantFiled: June 21, 2010Date of Patent: July 10, 2012Assignee: SanDisk Technologies Inc.Inventors: Chih-Chin Liao, Han-Shiao Chen, Chin-Tien Chiu, Ken Jian Ming Wang, Cheeman Yu, Hem Takiar
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Publication number: 20120164828Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.Type: ApplicationFiled: March 2, 2012Publication date: June 28, 2012Inventors: Hem Takiar, Cheeman Yu, Ken Jian Ming Wang, Chin-Tien Chiu, Han-Shiao Chen, Chih-Chin Liao
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Patent number: 8193613Abstract: According to one embodiment, a semiconductor die having increased usable area has at least six sides. The semiconductor die has a reduced stress at each corner of the die, resulting in smaller keep out zones near the corners of the semiconductor die, which allow the placement of bond pads near each corner of the die. The semiconductor die further allows the placement of active circuitry near each corner of the semiconductor die. One embodiment results in a 5.0% increase in usable area on the semiconductor die.Type: GrantFiled: March 6, 2007Date of Patent: June 5, 2012Assignee: Broadcom CorporationInventors: Ken Jian Ming Wang, Ming Wang Sze
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Patent number: 8129272Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.Type: GrantFiled: June 29, 2009Date of Patent: March 6, 2012Assignee: SanDisk Technologies Inc.Inventors: Hem Takiar, Cheeman Yu, Ken Jian Ming Wang, Chin-Tien Chiu, Han-Shiao Chen, Chih-Chin Liao
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Patent number: 7967184Abstract: A semiconductor package having a low profile is disclosed. In embodiments, a surface mounted component may be mounted directly to the core of the semiconductor package substrate, so that there is no conductive layer, plating layers or solder paste between the component and the substrate core. The surface mounted component may be any type of component which may be surface mounted on a substrate according to an SMT process, including for example passive components and various packaged semiconductors.Type: GrantFiled: November 16, 2005Date of Patent: June 28, 2011Assignee: SanDisk CorporationInventors: Chih-Chin Liao, Ken Jian Ming Wang, Han-Shiao Chen, Chin-Tien Chiu, Jack Chang Chien, Shrikar Bhagath, Cheemen Yu, Hem Takiar
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Patent number: 7872335Abstract: Methods and apparatus for integrated circuit (IC) packages with improved thermal performance and input/output capabilities are described. An integrated circuit (IC) package includes a leadframe, an IC die, a substrate having opposing first and second surfaces, a first wirebond, and a second wirebond. The leadframe includes a die attach pad having opposing first and second surfaces and a plurality of leads that emanate in an outward direction from the die attach pad. The IC die is coupled to the first surface of the die attach pad. The substrate is coupled to the die attach pad. Contact pads on the first surface of the substrate are electrically connected to bond fingers on the second surface of the substrate. The first wirebond couples a first bond pad on a first surface of the IC die to a bond finger on the second surface of the substrate. The second wirebond couples a second bond pad on the first surface of the IC die to a lead of the plurality of leads.Type: GrantFiled: November 30, 2007Date of Patent: January 18, 2011Assignee: Broadcom CorporationInventors: Rezaur Rahman Khan, Ken Jian Ming Wang