Abstract: A time measuring apparatus 10 includes a digital counter 20 that outputs a count signal in response to a clock signal, a plurality of TAC circuits 12 (TAC circuits 12a to 12j) to which a detection signal detected by a detector 4 and a clock signal are input and which output measurement signals corresponding to a time between the detection signal and the clock signal, a control unit 14 that derives and outputs time information related to the detection signal based on the count signal output from the digital counter 20 and the measurement signals output from the TAC circuits 12, and a measurement gate 11 that switches between the TAC circuits 12 to which the detection signal is input, in consideration of dead times of the TAC circuits 12.

Abstract: A time measurement device for calculating a time from an input of a first trigger signal to an input of a second trigger signal as a measured time includes a start gate configured to generate a start signal, a stop gate configured to generate a stop signal, a TDC circuit configured to generate a digital code corresponding to the time from an input of a start signal to an input of a stop signal, a delay circuit configured to delay an input of at least one of the start signal and the stop signal to the TDC circuit by a predetermined delay time, and a control unit configured to calculate a measured time on the basis of a plurality of digital codes generated by the TDC circuit, wherein the time delay unit selects at least two delay times.

Abstract: A time measurement device for calculating a time from an input of a first trigger signal to an input of a second trigger signal as a measured time includes a start gate configured to generate a start signal, a stop gate configured to generate a stop signal, a TDC circuit configured to generate a digital code corresponding to the time from an input of a start signal to an input of a stop signal, a delay circuit configured to delay an input of at least one of the start signal and the stop signal to the TDC circuit by a predetermined delay time, and a control unit configured to calculate a measured time on the basis of a plurality of digital codes generated by the TDC circuit, wherein the time delay unit selects at least two delay times.