Abstract: One embodiment of the present invention provides a ring oscillator with a digitally programmable frequency. This ring oscillator includes an odd number of inverting stages coupled input to output to form a ring, and a programming mechanism configured to digitally program the drive strength for each inverting stage in the ring oscillator, thereby changing the propagation delay between inverting stages and thereby allowing the frequency of the ring oscillator to be adjusted. In a variation on this embodiment, a given inverting stage includes a plurality of tri-state inverters coupled in parallel, so that inputs of the tri-state inverters are coupled to a common input for the given inverting stage, and outputs of the tri-state inverters are coupled to a common output for the given inverting stage. Moreover, each of the tri-state inverters can be selectively enabled, thereby allowing the drive strength of the given inverting stage to be adjusted.

Abstract: One embodiment of the present invention provides a system that facilitates fully characterizing propagation delay through an n-input circuit. The system operates by first receiving the n-input circuit. Next, the system establishes programmable voltage sources at each input of the n-input circuit. The system then programs each programmable voltage source to provide a sequence of input patterns to the n-input circuit. This sequence includes the 22n possible transitions between all possible pairs of input patterns. Next, the system measures the propagation delay between the input and the output of the n-input circuit for each transition in the sequence of input patterns and then reports the results.

Abstract: One embodiment of the present invention provides a system that facilitates fully characterizing propagation delay through an n-input circuit. The system operates by first receiving the n-input circuit. Next, the system establishes programmable voltage sources at each input of the n-input circuit. The system then programs each programmable voltage source to provide a sequence of input patterns to the n-input circuit. This sequence includes the 22n possible transitions between all possible pairs of input patterns. Next, the system measures the propagation delay between the input and the output of the n-input circuit for each transition in the sequence of input patterns and then reports the results.

Abstract: One embodiment of the present invention provides a ring oscillator with a digitally programmable frequency. This ring oscillator includes an odd number of inverting stages coupled input to output to form a ring, and a programming mechanism configured to digitally program the drive strength for each inverting stage in the ring oscillator, thereby changing the propagation delay between inverting stages and thereby allowing the frequency of the ring oscillator to be adjusted. In a variation on this embodiment, a given inverting stage includes a plurality of tri-state inverters coupled in parallel, so that inputs of the tri-state inverters are coupled to a common input for the given inverting stage, and outputs of the tri-state inverters are coupled to a common output for the given inverting stage. Moreover, each of the tri-state inverters can be selectively enabled, thereby allowing the drive strength of the given inverting stage to be adjusted.

Abstract: A method for a plus one operation includes dividing a binary number into bit sets including a least significant bit set, incrementing the least significant bit set, and, for each bit set other than the least significant bit set, incrementing the bit set unless any less significant bit sets comprises a zero. The bit sets are increment in one of two ways. If all bits of the bit set equal one, e.g., the bit set is 1111, then all bits of the bit set are simply complemented, sometimes called inverted, and set to zero. In all other instances, the least significant zero of the bit set is identified, and the least significant zero and all less significant bits, i.e., everything to the right of the least significant zero, is (are) complemented.

Abstract: A circuit for a plus one operation includes a means for incrementing a first bit set of a binary number and a means for detecting a zero in any bit set less significant than the first bit set, the means for detecting being coupled to the means for incrementing. The means for incrementing operates in a first mode when the means for detecting detects a zero in any bit set less significant than the first bit set and operates in a second mode when the means for detecting does not detect a zero in any bit set less significant than the first bit set.