Abstract: A stator of an electric motor includes a stator core including an annular yoke. The stator core includes a plurality of teeth formed on, for example, an inner periphery of the yoke and has a coil wound on each of the teeth. Each of the teeth includes first and second end portions opposed to each other in a radial direction of the stator core. The first end portion is connected to the yoke. The second end portion is formed with an axially extending projection extending in an axial direction of the stator core. A coil receiving groove is defined between the axially extending projection and the yoke. The axially extending projection includes a distal end portion in the axial direction, and a root portion adjoining a bottom of the coil receiving groove. In the radial direction, a thickness of the root portion is greater than a thickness of the distal end portion.

Abstract: A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside.

Abstract: In an electric power steering apparatus which includes a brushless motor composed of a cylindrical motor case with a bottom; a bracket for covering an opening of the motor case; an end housing for supporting a non-output-shaft side bearing located on one side; a bus bar housing in a ring shape for storing a plurality of bus bars; and a rotational angle sensor, and drives the brushless motor with a flow of current according to the detected steering torque, the end housing has a cylindrical section with a flange surrounding the end on one side and is inserted into the motor case from the opening until the flange comes into contact with the bottom of the motor case, the bus bar housing is placed to surround the outer circumferential surface of the cylindrical section of the end housing, and the rotational angle sensor is placed in the cylindrical section.

Abstract: The invention provides a motor including: a cylindrical motor case having a bottom that supports an outer circumferential surface of a stator core by an inner circumferential surface thereof; and a bracket that supports an output shaft side bearing and closes an opening of the motor case; wherein the stator core is press-fitted into the motor case from the opening such that a part of the stator core is exposed from the motor case, and a part of the stator core that is not press-fitted to the motor case forms a sliding fitting wall capable of providing a sliding fitting connection with the bracket.

Abstract: An electric power steering assembly includes an electric motor, a reduction mechanism for reducing the speed of an output rotation of the electric motor, and a reduction-mechanism housing accommodating therein the reduction mechanism. The electric motor includes: an output shaft rotatably supported by the reduction-mechanism housing, a motor housing formed integrally with the reduction-mechanism housing, a rotor, and a stator assembly accommodated in an annular space defined between the rotor and the motor housing. When the stator assembly is assembled in the annular space via an opening at an end portion of the motor housing, a guided portion on an outside circumference of a stator yoke is guided by a guide portion on an inside circumference of the motor housing.

Abstract: An electric power steering system is provided which is capable of providing a favorable steering feeling without using compensation logics such as of inertia compensation and friction compensation. The electric power steering system includes road-noise suppression control means (213) for controlling a steering assist motor (9) in a manner to damp torque transmission in a higher frequency region representing road noises than a frequency region representing road information. A friction value of a steering mechanism (A) is decreased enough to allow the intrinsic vibrations of the steering mechanism (A) to appear. Rotor inertia of the steering assist motor (9) is set to a value small enough to allow the frequencies of the intrinsic vibrations to be present in the frequency region where the torque transmission is damped by the road-noise suppression control means (213).

Abstract: An electric power steering assembly includes an electric motor, a reduction mechanism for reducing the speed of an output rotation of the electric motor, and a reduction-mechanism housing accommodating therein the reduction mechanism. The electric motor includes: an output shaft rotatably supported by the reduction-mechanism housing, a motor housing formed integrally with the reduction-mechanism housing, a rotor, and a stator assembly accommodated in an annular space defined between the rotor and the motor housing. When the stator assembly is assembled in the annular space via an opening at an end portion of the motor housing, a guided portion on an outside circumference of a stator yoke is guided by a guide portion on an inside circumference of the motor housing.

Abstract: Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough.

Abstract: Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough.

Abstract: An electric power steering device (1) includes a steering assist electric motor (7) including a rotation shaft (8) and a motor housing (18). The electric motor (7) includes a stator (19) fixed to the motor housing (18), a rotor (20) co-rotatable with the rotation shaft (8), and rotation angle detecting means (21) for detecting the rotation angle of the rotor (20). The rotation angle detecting means (21) includes a stationary portion (28) fixed to the motor housing (18), and a movable portion (29) co-rotatable with the rotor (20). The rotor (20) includes a rotor body (31), and a rotor magnet (32) attached to the rotor body (31) in a co-rotatable manner. A rotor unit (33) including the rotor (20) and the movable portion (29) of the rotation angle detecting means (21) is provided as a subassembly of the electric motor (7).

Abstract: A semiconductor storage device which includes a memory array including a plurality of memory cells for storing data by using a difference in a threshold voltage and at least one reference cell for storing data indicative of a state of a corresponding memory cell by using a difference in a threshold voltage, a control circuit for determining a read voltage based on data stored by a reference cell corresponding to a memory cell adjacent to a memory cell to be read, a read unit for executing reading from a memory cell to be read by using a determined read voltage, and a write unit for executing writing, when executing writing to a memory cell to be written to bring the memory cell into a written state, data indicating that the memory cell is in the written state to a reference cell corresponding to the memory cell.

Abstract: A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order.

Abstract: The disclosed flash memory is provided with a majority logic circuit 3 and shift registers 61 to 63. Three out of the banks 2a to 2c of the memory respectively include management information areas KAs to store binary management information comprising power supply trimming data and bitline restoration data. During initialization of the flash memory, the majority logic circuit 3 performs error correction on management information bits retrieved from the management information areas KAs and outputs that information to a trimming/restoration data buffer 11, thus providing highly reliable management information very quickly. The shift registers 61 to 63 delay a control signal that is output from a control circuit 12 by a certain period of time before outputting the control signal to sense amplifiers 42 to 44. This delay makes it possible to make the operating currents of the banks 2a to 2d start to flow at different times and to suppress a peak current flowing in the flash memory.

Abstract: An electrically writable/erasable nonvolatile semiconductor memory such as an AND-type or NOR-type flash memory having an array structure, in which numerous memory cells are connected in parallel between common bit lines and source lines, is capable of readily detecting a memory cell in depletion failure which occurs in the event of a power supply cutoff during a memory cell threshold voltage shift-down operation by the writing or erasing operation. In operation, at the entry of a certain command or at the time of power-on, all word lines are unselected and bit line selecting switches are turned on to find the presence of a memory cell having a current flow due to depletion failure with sense amplifiers connected to the bit lines. On finding the presence of a failing cell, a voltage of selection level (VSS or negative voltage) is applied to each word line in turn, with remaining word lines being pulled to an unselection voltage level (negative voltage or VSS).

Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.

Abstract: A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order.

Abstract: A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order.

Abstract: While light of R, G and B is switched from one to another and directed to a plurality of light shutter elements made of PLZT, a voltage is applied in accordance with image data between individual electrodes for the respective light shutter elements and a common electrode for all the light shutter elements. While a half-wave voltage Vr for light of R is applied to the individual electrodes, the voltage applied to the common electrode is altered to 0V, Vr-Vg and Vr-Vb in synchronization with switch of the three primary colors so that half-wave voltages for the respective colors can be applied to the light shutter elements.

Abstract: A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside.

Abstract: An electric power steering assembly includes an electric motor, a reduction mechanism for reducing the speed of an output rotation of the electric motor, and a reduction-mechanism housing accommodating therein the reduction mechanism. The electric motor includes: an output shaft rotatably supported by the reduction-mechanism housing, a motor housing formed integrally with the reduction-mechanism housing, a rotor, and a stator assembly accommodated in an annular space defined between the rotor and the motor housing. When the stator assembly is assembled in the annular space via an opening at an end portion of the motor housing, a guided portion on an outside circumference of a stator yoke is guided by a guide portion on an inside circumference of the motor housing.