Patents by Inventor Ken Mimuro
Ken Mimuro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8421176Abstract: A solid-state image pickup device relating to the present invention has a specific gap in a part of a lattice-shaped light blocking film pattern or wiring pattern having an opening enclosing a light reception region. Peripheral circuits and wiring layers on a pixel may be used as the light blocking film. In such a case, when multiple wiring layers are used as the light blocking film, layouts of a second and subsequent wiring layers is determined according to the layout of the first wiring layer above the light reception region. The specific gap is created in a part of the wiring enclosing the light reception region.Type: GrantFiled: September 15, 2009Date of Patent: April 16, 2013Assignee: Panasonic CorporationInventors: Ken Mimuro, Jun Jisaki
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Publication number: 20100078748Abstract: A solid-state image pickup device relating to the present invention has a specific gap in a part of a lattice-shaped light blocking film pattern or wiring pattern having an opening enclosing a light reception region. Peripheral circuits and wiring layers on a pixel may be used as the light blocking film. In such a case, when multiple wiring layers are used as the light blocking film, layouts of a second and subsequent wiring layers is determined according to the layout of the first wiring layer above the light reception region. The specific gap is created in a part of the wiring enclosing the light reception region.Type: ApplicationFiled: September 15, 2009Publication date: April 1, 2010Inventors: Ken MIMURO, Jun JISAKI
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Patent number: 7675327Abstract: The semiconductor device of the present invention includes a bootstrap circuit, the bootstrap circuit including: a selection transistor composed of an n-channel MOS transistor; a booster transistor of which a gate is connected to a drain of the selection transistor; and a boosting circuit that is connected between the gate and a source of the booster transistor, and boosts gate voltage with respect to the source of the booster transistor, wherein gate dimensions of the selection transistor are smaller than gate dimensions of the booster transistor. According to this configuration, the semiconductor device can realize increasing an action of a circuit, decreasing a chip size and simplifying processes.Type: GrantFiled: May 12, 2006Date of Patent: March 9, 2010Assignee: Panasonic CorporationInventors: Ken Mimuro, Mikiya Uchida
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Patent number: 7550814Abstract: A solid-state imaging device including: a plurality of photosensitive cells, each having a photodiode, arranged on a semiconductor substrate (1) in a matrix; and a peripheral driving circuit that has a plurality of transistors for driving the plurality of photosensitive cells. The plurality of transistors includes a first transistor and a second transistor, the first transistor having a first diffusion layer (2) as a source or a drain where a signal potential corresponding to a signal charge generated by the photodiode is transmitted and held, and the second transistor having a second diffusion layer as a source and a drain where the signal potential is not transmitted.Type: GrantFiled: October 28, 2005Date of Patent: June 23, 2009Assignee: Panasonic CorporationInventors: Mikiya Uchida, Ken Mimuro, Mototaka Ochi
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Patent number: 7329557Abstract: A solid-state imaging device includes: a plurality of N-type photodiode regions formed inside a P-type well; a gate electrode having one edge being positioned adjacent to each of the photodiode regions; a N-type drain region positioned adjacent to the other edge of the gate electrode; an element-isolating portion having a STI structure, and a gate oxide film having a thickness of not more than 10 nm. One edge of the gate electrode overlaps the photodiode region.Type: GrantFiled: February 10, 2006Date of Patent: February 12, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ken Mimuro, Mikiya Uchida, Mototaka Ochi
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Publication number: 20070290286Abstract: A solid-state imaging device including: a plurality of photosensitive cells, each having a photodiode, arranged on a semiconductor substrate (1) in a matrix; and a peripheral driving circuit that has a plurality of transistors for driving the plurality of photosensitive cells. The plurality of transistors includes a first transistor and a second transistor, the first transistor having a first diffusion layer (2) as a source or a drain where a signal potential corresponding to a signal charge generated by the photodiode is transmitted and held, and the second transistor having a second diffusion layer as a source and a drain where the signal potential is not transmitted.Type: ApplicationFiled: October 28, 2005Publication date: December 20, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Mikiya Uchida, Ken Mimuro, Mototaka Ochi
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Publication number: 20070228495Abstract: An integrated circuit includes: a semiconductor substrate that has a well region containing a first conductivity type impurity; and an enhancement type MOS transistor and a plurality of depletion type MOS transistors, each of which is formed in the well region and has a channel region under a gate electrode. At least one of the depletion type MOS transistors has, in the channel region, an implantation region into which a second conductivity type impurity is implanted so that a threshold voltage is adjusted. The implantation region has the first conductivity type impurity and the second conductivity type impurity. Further, the second conductivity type impurity has a concentration that is higher than a concentration of the first conductivity type impurity.Type: ApplicationFiled: November 21, 2006Publication date: October 4, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Chinatsu SETO, Mikiya UCHIDA, Ken MIMURO, Emi KANAZAKI
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Publication number: 20070040583Abstract: The semiconductor device of the present invention includes a bootstrap circuit, the bootstrap circuit including: a selection transistor composed of an n-channel MOS transistor; a booster transistor of which a gate is connected to a drain of the selection transistor; and a boosting circuit that is connected between the gate and a source of the booster transistor, and boosts gate voltage with respect to the source of the booster transistor, wherein gate dimensions of the selection transistor are smaller than gate dimensions of the booster transistor. According to this configuration, the semiconductor device can realize increasing an action of a circuit, decreasing a chip size and simplifying processes.Type: ApplicationFiled: May 12, 2006Publication date: February 22, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Ken Mimuro, Mikiya Uchida
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Publication number: 20060128052Abstract: A solid-state imaging device includes: a plurality of N-type photodiode regions formed inside a P-type well; a gate electrode having one edge being positioned adjacent to each of the photodiode regions; a N-type drain region positioned adjacent to the other edge of the gate electrode; an element-isolating portion having a STI structure, and a gate oxide film having a thickness of not more than 10 nm. One edge of the gate electrode overlaps the photodiode region.Type: ApplicationFiled: February 10, 2006Publication date: June 15, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Ken Mimuro, Mikiya Uchida, Mototaka Ochi
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Patent number: 7030433Abstract: A solid-state imaging device includes: a plurality of N-type photodiode regions formed inside a P-type well; a gate electrode having one edge being positioned adjacent to each of the photodiode regions; a N-type drain region positioned adjacent to the other edge of the gate electrode; an element-isolating portion having a STI structure, and a gate oxide film having a thickness of not more than 10 nm. One edge of the gate electrode overlaps the photodiode region.Type: GrantFiled: October 8, 2004Date of Patent: April 18, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ken Mimuro, Mikiya Uchida, Mototaka Ochi
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Publication number: 20050082631Abstract: A solid-state imaging device includes: a plurality of N-type photodiode regions formed inside a P-type well; a gate electrode having one edge being positioned adjacent to each of the photodiode regions; a N-type drain region positioned adjacent to the other edge of the gate electrode; an element-isolating portion having a STI structure, and a gate oxide film having a thickness of not more than 10 nm. One edge of the gate electrode overlaps the photodiode region.Type: ApplicationFiled: October 8, 2004Publication date: April 21, 2005Applicant: Matsushita Electric industrial Co., Ltd.Inventors: Ken Mimuro, Mikiya Uchida, Mototaka Ochi
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Patent number: 6753222Abstract: A method for forming a semiconductor device is provided that allows a desirable semiconductor device to be obtained by preventing a gate electrode of a non-volatile semiconductor memory from having an abnormal shape and the surfaces of high concentration source and drain regions of the non-volatile semiconductor memory from being worn away. The method includes a first step of forming a non-volatile semiconductor memory in a first region of a substrate of the semiconductor device and a second step of forming a semiconductor device in a second region on the substrate. The non-volatile semiconductor memory includes a first gate including a tunnel insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode, and the semiconductor device includes a second gate including a gate insulating film and a gate electrode.Type: GrantFiled: October 15, 2002Date of Patent: June 22, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ken Mimuro, Hiroyuki Doi, Yasushi Okuda
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Publication number: 20030082878Abstract: A method for forming a semiconductor device is provided that allows a desirable semiconductor device to be obtained by preventing a gate electrode of a non-volatile semiconductor memory from having an abnormal shape and the surfaces of high concentration source and drain regions of the non-volatile semiconductor memory from being worn away. The method includes a first step of forming a non-volatile semiconductor memory in a first region of a substrate of the semiconductor device and a second step of forming a semiconductor device in a second region on the substrate. The non-volatile semiconductor memory includes a first gate including a tunnel insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode, and the semiconductor device includes a second gate including a gate insulating film and a gate electrode.Type: ApplicationFiled: October 15, 2002Publication date: May 1, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Ken Mimuro, Hiroyuki Doi, Yasushi Okuda