Abstract: A water dance device with display screen effect primarily comprises a box body therein are disposed a rotating water spray unit, a swinging water spray unit, a multicolored water spray unit, an intermittent water spray unit, a fogging device, and a laser projector. The rotating water spray unit and the swinging water spray unit are disposed to provide rotating and swinging water jets; the multicolored water spray unit is disposed to provide water jets of various colors; the intermittent water spray unit is disposed to provide single projectile water jets; and the fogging device is disposed to provide a foggy veil for the laser projector to project texts or images thereon. Providing various forms of water dance performance composed in its box body and advertising effect, the present invention may be placed in businesses, stores and shops for achieving the purpose of attracting potential customers.

Abstract: An atomizing cooling structure attachable to an umbrella comprises primarily a main body therein are disposed a holding tank and a water storage tank segmented from each other, wherein in the holding tank are disposed a control circuit and an ultrasonic oscillating element which extends to the water storage tank with an absorptive bar and corresponds to a release vent disposed on the holding tank; when in use, the main body is clamped onto an umbrella rib of an umbrella or any position below an umbrella canopy, and after the control circuit is turned on, the absorptive bar picks up water from the water storage tank, which is oscillated by the ultrasonic oscillating element and turned into water mist to be released from the release vent and float beneath the umbrella for providing cooling effect on hot summer days.

Abstract: A water dance device with display screen effect primarily comprises a box body therein are disposed a rotating water spray unit, a swinging water spray unit, a multicolored water spray unit, an intermittent water spray unit, a fogging device, and a laser projector. The rotating water spray unit and the swinging water spray unit are disposed to provide rotating and swinging water jets; the multicolored water spray unit is disposed to provide water jets of various colors; the intermittent water spray unit is disposed to provide single projectile water jets; and the fogging device is disposed to provide a foggy veil for the laser projector to project texts or images thereon. Providing various forms of water dance performance composed in its box body and advertising effect, the present invention may be placed in businesses, stores and shops for achieving the purpose of attracting potential customers.

Abstract: A music box structure with composing function comprises primarily a comb reed composed of teeth which are tuned to play various musical notes, a motor-driven cylinder, and a plurality of pins, wherein on a surface of the cylinder are disposed a plurality of spaced jack holes corresponding to the teeth of the comb reed. When in use, a user may insert pins into various jack holes on the cylinder according to various music scores or the user's own composition with the inserted pins having an appropriate protrusion height. When the cylinder is driven to rotate by the motor, the inserted pins pluck the teeth at various positions on the comb reed in order and produce music.

Abstract: A method for transmitting audio data of a plurality of audio sources through a single SPDIF link, includes: sequencing and multiplexing the audio data of the plurality of audio sources to pack the audio data of the plurality of audio sources into a plurality of frames of a block; performing bi-phase mark encoding on the audio data in the frames; appending preambles Z, X, and Y of the AES3/SPDIF stream format to the frames according to the number of audio sources in a first mode, or appending preambles Z, X, and Y of the AES3/SPDIF stream format and a specific preamble differing from preambles Z, X, and Y to the frames according to the number of audio sources in a second mode; and outputting the frames carrying the audio data into the SPDIF link with a frame rate greater than an audio sampling frequency of one of the audio sources.

Abstract: A digital lock detector for a phase-locked loop. The PLL generates a feedback clock according to a reference clock. The digital lock detector includes a match detector and an arbiter. When a first clock transitions, the match detector checks that whether a second clock transitions in a predetermined time window or not. The match detector generates a match signal if the second clock transitions in the predetermined time window. The arbiter counts a number of the successive match signals and generates a lock signal to indicate a lock state when the number exceeds a first predetermined number.

Abstract: Dual-function drivers capable of outputting LVDS or TMDS differential signals by sharing output terminals under differential modes. In the dual-function driver, an input control unit receives a first input signal compliant with a first specification in a first mode and a second input signal compliant with a second specification in a second mode by sharing a pair of input terminals, and a current steering circuit comprises first and second differential pairs. The input control unit enables the first and second differential pairs to output a first differential signal compliant with the first specification through a pair of output terminals during the first mode, and the input control unit disables the first differential pair and enables the second differential pair to output a second differential signal compliant with the second specification on the pair of output terminals during the second mode.

Abstract: A combined transmission unit for TMDS signals and LVDS signals. A first (LVDS) transmission unit comprises a set of first input terminals to receive first data, and a second (TMDS) transmission unit comprises a set of second input terminals to receive second data. A switching controller enables the first transmission unit to transmit the first data to the first external input units through a pair of signal lines coupled to a set of common output line or enables the second transmission unit to transmit the second data to the second external input units through a pair of signal lines coupled to the set of common output line, according to a mode selection signal.

Abstract: A delay locked loop circuit for delaying an input clock to lock a delay clock. The delay locked loop includes a frequency divider for dividing a frequency of the input clock by a number N to obtain a frequency-divided clock, a plurality of delay components for delaying the input clock to generate a plurality of delay clocks with different phase according to a count value, a phase detector coupled to a final delay components for detecting a phase transition between a final delay clock and the input clock, and a counter coupled to the phase detector and the frequency divider for generating the count value according to the phase transition between the final delay clock and the input clock.

Abstract: A power bus for use in an IC is disclosed that is configured as a grid and further formed using strips formed on I/O pads such as data I/O and multi-level voltage I/O pads. An IC is disclosed comprising a power supply I/O pad and a data I/O pad which are made of a deposited conductor. The power supply I/O pad is connected to a power bus and the data I/O pad is connected to circuitry. A strip of deposited conductor is formed closely adjacent to the data I/O pad wherein the strip is connected to the power bus. Parallel paths are developed within the integrated circuit to distribute power within the circuit. A similar approach is taken with respect to multi-level I/O pads. The power bus provide for reduced IR drops and better power supplies to core logic within an integrated circuit.

Abstract: A LVDS and TMDS dualfunction transmitter for both LVDS and TMDS output channels is disclosed, including an encoder and a serializer. The encoder encodes twenty eight bits of LVDS signals to thirty bits of TMDS signals. The serializer includes four serializer channels for converting the LVDS signals to a serial signal when a LVDS mode is enabled, or converting the TMDS signals to the serial signal when a TMDS mode is enabled. Wherein a first serializer channel is coupled to seven bits of the LVDS signals and outputting a first pair of differential signals. Second, third and fourth serializer channel are coupled to seven bits of the LVDS signals and ten bits of TMDS signals, and outputting a second, third and fourth pair of differential signals, respectively.

Abstract: A combined transmission unit for TMDS signals and LVDS signals. First (LVDS) and second (TMDS) transmission units are both coupled to a first set of input terminals. A switching controller, according to a mode selection signal, enables the first transmission unit to transmit the first data on the set of input terminals to first external input units through a pair of first signal lines or enables the second transmission unit to transmit the first data on the set of input terminals to the second external input units through a pair of second signal lines.

Abstract: A method for transmitting audio data of a plurality of audio sources through a single SPDIF link, includes: sequencing and multiplexing the audio data of the plurality of audio sources to pack the audio data of the plurality of audio sources into a plurality of frames of a block; performing bi-phase mark encoding on the audio data in the frames; appending preambles Z, X, and Y of the AES3/SPDIF stream format to the frames according to the number of audio sources in a first mode, or appending preambles Z, X, and Y of the AES3/SPDIF stream format and a specific preamble differing from preambles Z, X, and Y to the frames according to the number of audio sources in a second mode; and outputting the frames carrying the audio data into the SPDIF link with a frame rate greater than an audio sampling frequency of one of the audio sources.

Abstract: An apparatus for compensating for glitch occurrence in a reset signal that is applied in an integrated circuit, includes: a logic stage capable to process an incoming signal and a delayed incoming signal that is a delayed version of the incoming signal, the logic stage capable to generate an output signal so that when the incoming signal and the delayed incoming signal are in the same state, the output signal will be in the same state.

Abstract: A combined output driver for TMDS signals and LVDS signals. First and second output drivers output first and second differential signals to a first external input unit and a second external input unit, respectively, through a pair of signal lines according to first and second input signals. In the second output driver, a driver buffer is coupled to a first voltage and a first node respectively to generate two control signals according to the second input signals. An output unit generates the second differential signal according to the two control signals. A power supply provides a second voltage higher than the first voltage to power the driver buffer and the output unit when the first output driver outputs the first differential signal to the first external input unit.

Abstract: A combined output driver for TMDS signals and LVDS signals. A first output driver includes a first differential unit generating a first differential according to first input signals in a first mode and a first clamping device coupled between the first node and the first differential unit to clamp potentials at two power terminals below a second power voltage. The second output driver includes a second differential unit generating a second differential signal according to second input signals in a second mode and a second clamping device to clamp potentials at two output terminals of the second differential unit below the second power voltage.

Abstract: Dual-function drivers capable of outputting LVDS or TMDS differential signals by sharing output terminals under differential modes. In the dual-function driver, an input control unit receives a first input signal compliant with a first specification in a first mode and a second input signal compliant with a second specification in a second mode by sharing a pair of input terminals, and a current steering circuit comprises first and second differential pairs. The input control unit enables the first and second differential pairs to output a first differential signal compliant with the first specification through a pair of output terminals during the first mode, and the input control unit disables the first differential pair and enables the second differential pair to output a second differential signal compliant with the second specification on the pair of output terminals during the second mode.

Abstract: A combined transmission unit for TMDS signals and LVDS signals. A first (LVDS) transmission unit includes a set of first input terminals to receive first data, and a second (TMDS) transmission unit includes a set of second input terminals to receive second data. A phase locked loop (PLL) generates a first set of output clock signals to the first transmission unit in a first mode and a second set of output clock signals to the second transmission unit in a second mode according to a mode selection signal. The first and second transmission units are able to transmit the first data to the first and second external input units in the first and second modes respectively, according to the mode selection signal and the first and second sets of output clock signals.

Abstract: A LVDS and TMDS dualfunction transmitter for both LVDS and TMDS output channels is disclosed, including an encoder and a serializer. The encoder encodes twenty eight bits of LVDS signals to thirty bits of TMDS signals. The serializer includes four serializer channels for converting the LVDS signals to a serial signal when a LVDS mode is enabled, or converting the TMDS signals to the serial signal when a TMDS mode is enabled. Wherein a first serializer channel is coupled to seven bits of the LVDS signals and outputting a first pair of differential signals. Second, third and fourth serializer channel are coupled to seven bits of the LVDS signals and ten bits of TMDS signals, and outputting a second, third and fourth pair of differential signals, respectively.

Abstract: A delay locked loop circuit for delaying an input clock to lock a delay clock. The delay locked loop includes a frequency divider for dividing a frequency of the input clock by a number N to obtain a frequency-divided clock, a plurality of delay components for delaying the input clock to generate a plurality of delay clocks with different phase according to a count value, a phase detector coupled to a final delay components for detecting a phase transition between a final delay clock and the input clock, and a counter coupled to the phase detector and the frequency divider for generating the count value according to the phase transition between the final delay clock and the input clock.