Patents by Inventor Ken Numata
Ken Numata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100244027Abstract: A semiconductor device includes a capacitor element that stores charge to perform as a memory that stores information. The capacitor may include, but is not limited to, an insulating layer, a first electrode, and a second electrode. The insulating layer includes metal oxide. The insulating layer has a high dielectric constant. The first electrode contacts with a first surface of the insulating layer. The first electrode is made of a first conductive material including at least one of precious metals and compounds thereof. The second electrode contacts with a second surface of the insulating layer. The second electrode is made of a second conductive material including at least one of metals and compounds thereof. The metals are different from the precious metals. The second conductive material is lower in work function than the first conductive material. The first electrode is lower in potential than the second electrode.Type: ApplicationFiled: March 25, 2010Publication date: September 30, 2010Applicant: ELPIDA MEMORY, INC.Inventor: Ken Numata
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Patent number: 6472229Abstract: The purpose of this invention is to provide a method for manufacturing capacitors free of polarization fatigue even when the treatment is performed at a low temperature. Amorphous layer 32 made of lead zirconate titanate and containing excess lead is formed on lower electrode 13 made of iridium. The amorphous layer is crystallized by a heat treatment to form PZT film 14. Structural transition layer 33 containing excess Pb formed on the surface of PZT film 14 during the aforementioned crystallization is removed by means of dry etching. In this way, a PZT capacitor is obtained.Type: GrantFiled: June 5, 1998Date of Patent: October 29, 2002Assignee: Texas Instruments IncorporatedInventors: Katsuhiro Aoki, Yukio Fukuda, Ken Numata
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Patent number: 6404664Abstract: A twisted bit line structure (89) in an integrated memory circuit, and method for making it are presented. The structure is constructed by forming bit line traces (90, 92, 94, 96) on an integrated circuit substrate (88) using phase shift lithography techniques. Using these techniques, the bit line traces are arranged with a plurality of substantially parallel bit lines trace segments (90, 92, 94, 94′, 96, 96′) with discontinuous regions between segments of the interior pair (94, 94′; 96, 96′) of traces. Thus, each “phase &pgr;” bit line trace is adjacent a “phase 0” bit line trace.Type: GrantFiled: September 24, 1999Date of Patent: June 11, 2002Assignee: Texas Instruments IncorporatedInventor: Ken Numata
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Patent number: 6326695Abstract: A twisted bit line structure (69) in an integrated memory circuit, and method for making it are presented. The structure is constructed by forming bit line traces (70-73) on an integrated circuit substrate using phase shift lithography techniques. Using these techniques, the bit line traces are arranged with a plurality of substantially parallel bit lines trace segments (70, 70′; 71, 71′; 72, 72′; 73, 73′) with discontinuous regions between segments of each trace along a path substantially perpendicular to the bit line traces. Thus, each “phase &pgr;” bit line trace is adjacent a “phase 0” bit line trace along two perpendicular axes.Type: GrantFiled: September 23, 1999Date of Patent: December 4, 2001Assignee: Texas Instruments IncorporatedInventor: Ken Numata
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Patent number: 6297085Abstract: To provide a method that can be used to form a high-qualility ferroelectric film by forming good nuclei when using the sputtering method to manufacture a PZT capacitor or other forroelectric capacitors using Ir or other electrode substances in addition to Pt for the electrode. In the method for manufacturing a PZT ferroelectric capacitor CAP, after titanium film 31 is deposited on Ir electrode 6, lead oxide 32 is deposited at a substrate temperature higher than the crystallization temperature of lead titanate using the sputtering method. Lead zirconate titanate 34 is then deposited at a substrate temperature higher than the aforementioned substrate temperature using the sputtering temperature. Afterwards, a heat treatment of the deposited film is performed to produce PZT film 17.Type: GrantFiled: December 11, 1997Date of Patent: October 2, 2001Assignee: Texas Instruments IncorporatedInventors: Katsuhiro Aoki, Yukio Fukuda, Ikuko Murayama, Ken Numata, Akitoshi Nishimura
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Publication number: 20010022383Abstract: An isolation structure which protrudes above the semiconductor surface and sidewall spacers which smooth the topography over said isolation structure.Type: ApplicationFiled: May 1, 2001Publication date: September 20, 2001Inventors: Shigeru Kuroda, Yasutoshi Okuno, Ken Numata
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Patent number: 6251749Abstract: An isolation structure which protrudes above the semiconductor surface and sidewall spacers which smooth the topography over said isolation structure.Type: GrantFiled: September 13, 1999Date of Patent: June 26, 2001Assignee: Texas Instruments IncorporatedInventors: Shigeru Kuroda, Yasutoshi Okuno, Ken Numata
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Patent number: 6150183Abstract: A metal oxide capacitor is manufactured by sequentially laminating a metal oxide film and a secon electrode on a first electrode. The metal oxide film is formed and then heat-treated in an atmosphere with an oxygen pressure higher than 1 atm.Type: GrantFiled: December 18, 1997Date of Patent: November 21, 2000Assignee: Texas Instruments IncorporatedInventors: Yukio Fukuda, Katsuhiro Aoki, Akitoshi Nishimura, Ken Numata
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Patent number: 6033953Abstract: A dielectric capacitor is provided which has a reduced leakage current. The surface of a first electrode (38) of the capacitor is electropolished and a dielectric film (40) and a second electrode (37) are successively laminated on it. The convex parts pointed end (38a) existing on the surface of the first electrode is very finely polished uniformly by dissolving according to electropolishing, a spherical curved surface in which the radius of curvature has been enlarged is formed, and the surface of the first electrode is flattened. Therefore, concentration of electrolysis can be prevented during the operation at the interface of the first electrode and the dielectric film, and the leakage current can be reduced considerably.Type: GrantFiled: December 16, 1997Date of Patent: March 7, 2000Assignee: Texas Instruments IncorporatedInventors: Katsuhiro Aoki, Yukio Fukuda, Ken Numata, Yasutoshi Okuno, Akitoshi Nishimura
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Patent number: 5811352Abstract: A method for manufacturing semiconductor device having conductive metal leads 14 with improved reliability, and device for same, comprising conductive metal leads 14 on a substrate 12, a first insulating material 18 at least between the conductive metal leads 14, and dummy leads 16 proximate the conductive metal leads 14. Heat from the conductive metal leads 14 is transferable to the dummy leads 16, and the dummy leads 16 are capable of dissipating the heat. The first insulating material 18 has a dielectric constant of less than 3.5. An optional heatsink 22 may be formed in contact with the first dummy leads 16 to further dissipate the Joule's heat from the conductive metal leads 14. An advantage of the invention is to improve reliability of metal leads for circuits using low-dielectric constant materials.Type: GrantFiled: November 6, 1996Date of Patent: September 22, 1998Assignee: Texas Instruments IncorporatedInventors: Ken Numata, Kay Houston
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Patent number: 5793600Abstract: A capacitor and electrode structure comprising a PZT ferroelectric layer 17 with a primary component (Pb) and secondary component (Ti), a lower electrode layer 16 formed on the underside of the ferroelectric layer and made up of a special element (Pt) and Ti, and compounds thereof, and a diffusion barrier layer 18 which is formed on the underside of the lower electrode layer and which functions as a diffusion barrier with respect to Pb. The capacitor and the electrode structure, which may be a component of a semiconductor memory device, suppress fluctuations in the composition of the ferroelectric layer in PZT, etc., so as to maintain the intended performance of the PZT ferroelectric layer, thereby simplifying and stabilizing film fabrication, and preventing the degradation of electrical characteristics and adverse effects on lower layers.Type: GrantFiled: October 20, 1995Date of Patent: August 11, 1998Assignee: Texas Instruments IncorporatedInventors: Yukio Fukuda, Katsuhiro Aoki, Akitoshi Nishimura, Ken Numata
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Patent number: 5751056Abstract: A semiconductor device having metal leads 14 with improved reliability comprising metal leads 14 on a substrate 12, a low-dielectric constant material 18 at least between the metal leads 14, and dummy leads 16 proximate the metal leads 14. Heat from the metal leads 14 is transferable to the dummy leads 16, and the dummy leads 16 are capable of dissipating the heat. The low-dielectric constant material 18 has a dielectric constant of less than 3.5. An advantage of the invention is improved reliability of metal leads for circuits using low-dielectric constant materials.Type: GrantFiled: June 7, 1995Date of Patent: May 12, 1998Assignee: Texas Instruments IncorporatedInventor: Ken Numata
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Patent number: 5675187Abstract: A semiconductor device (and method of manufacturing thereof) having metal leads (114+130) with improved reliability, comprising metal leads (114+130) on a substrate 112, a low-dielectric constant material (116) at least between the metal leads (114+130), and dummy vias (122+134) in contact with the metal leads (114+130). Heat from the metal leads (114+130) is transferable to the dummy vias (122+134), and the dummy vias (122+134) are capable of conducting away the heat. The low-dielectric constant material (116) may have a dielectric constant of less than about 3.5. An advantage of the invention is to improve reliability of metal leads in circuits using low-dielectric constant materials, especially in scaled-down circuits that are compact in the horizontal direction.Type: GrantFiled: May 16, 1996Date of Patent: October 7, 1997Assignee: Texas Instruments IncorporatedInventors: Ken Numata, Kay L. Houston
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Patent number: 5654567Abstract: A capacitor, electrode, or wiring structure having an alpha ray emitting source (in particular, a Pt electrode), and an alpha ray shielding layer 18, having at least one type selected from the group of simple metals of nickel, cobalt, copper, and tungsten, their compounds or alloys made of at least two types of these simple metals, and compounds and alloys made of these simple metals and silicon is provided. It is possible to shield off the alpha ray effectively, to suppress generation of soft errors, to enable the use of Pt and other new materials in making the electrodes and wiring, and to reduce the cost of the mold resin.Type: GrantFiled: October 1, 1996Date of Patent: August 5, 1997Assignee: Texas Instruments IncorporatedInventors: Ken Numata, Katsuhiro Aoki, Yukio Fukuda, Akitoshi Nishimura
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Patent number: 5625232Abstract: A semiconductor device (and method of manufacturing thereof) having metal leads (114+130) with improved reliability, comprising metal leads (114+130) on a substrate 112, a low-dielectric constant material (116) at least between the metal leads (114+130), and dummy vias (122+134) in contact with the metal leads (114+130). Heat from the metal leads (114+130) is transferable to the dummy vias (122+134), and the dummy vias (122+134) are capable of conducting away the heat. The low-dielectric constant material (116) may have a dielectric constant of less than about 3.5. An advantage of the invention is to improve reliability of metal leads in circuits using low-dielectric constant materials, especially in scaled-down circuits that are compact in the horizontal direction.Type: GrantFiled: July 15, 1994Date of Patent: April 29, 1997Assignee: Texas Instruments IncorporatedInventors: Ken Numata, Kay L. Houston
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Patent number: 5519250Abstract: A method for manufacturing semiconductor device having metal leads 14 with improved reliability, and device for same, comprising metal leads 14 on a substrate 12, a low-dielectric constant material 18 at least between the metal leads 14, and thermoconductive insulating layer 22 deposited on the metal leads 14 and the low-dielectric constant material 18, and dummy leads 16 proximate metal leads 14. Heat from the metal leads 14 is transferable to the dummy leads 16 and thermoconductive insulating layer 22, which are both capable of dissipating the heat. A thin thermoconductive layer 24 may be deposited over the metal leads 14 prior to depositing at least the low-dielectric constant material 18 and the thermoconductive insulating layer 22. The low-dielectric constant material 18 has a dielectric constant of less than 3.5. An advantage of the invention is to improve reliability of metal leads for circuits using low-dielectric constant materials.Type: GrantFiled: June 7, 1995Date of Patent: May 21, 1996Inventor: Ken Numata
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Method of making reliable metal leads in high speed LSI semiconductors using thermoconductive layers
Patent number: 5510293Abstract: A method for manufacturing semiconductor device having metal leads 14 with improved reliability, and device for same, including metal leads 14 on a substrate 12, a low-dielectric constant material 18 at least between the metal leads 14, and thermoconductive insulating layer 22 deposited on the metal leads 14 and the low-dielectric constant material 18. Heat from the metal leads 14 is transferable to the thermoconductive insulating layer 22, and the thermoconductive insulating layer 22 is capable of dissipating the heat. The low-dielectric constant material 18 has a dielectric constant of less than 3.5. An advantage of the invention is to improve reliability of metal leads for circuits using low-dielectric constant materials.Type: GrantFiled: May 31, 1994Date of Patent: April 23, 1996Assignee: Texas Instruments IncorporatedInventor: Ken Numata -
Patent number: 5508953Abstract: A capacitor and electrode structure comprising a PZT ferroelectric layer 17 with a primary component (Pb) and secondary component (Ti), a lower electrode layer 16 formed on the underside of the ferroelectric layer and made up of a special element (Pt) and Ti, and compounds thereof, and a diffusion barrier layer 18 which is formed on the underside of the lower electrode layer and which functions as a diffusion barrier with respect to Pb. The capacitor and the electrode structure, which may be a component of a semiconductor memory device, suppress fluctuations in the composition of the ferroelectric layer in PZT, etc., so as to maintain the intended performance of the PZT ferroelectric layer, thereby simplifying and stabilizing film fabrication, and preventing the degradation of electrical characteristics and adverse effects on lower layers.Type: GrantFiled: May 16, 1994Date of Patent: April 16, 1996Assignee: Texas Instruments IncorporatedInventors: Yukio Fukuda, Katsuhiro Aoki, Akitoshi Nishimura, Ken Numata
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Patent number: 5476817Abstract: A method for manufacturing semiconductor device having metal leads 14 with improved reliability, and device for same, comprising metal leads 14 on a substrate 12, a low-dielectric constant material 18 at least between the metal leads 14, and thermoconductive insulating layer 22 deposited on the metal leads 14 and the low-dielectric constant material 18, and dummy leads 16 proximate metal leads 14. Heat from the metal leads 14 is transferable to the dummy leads 16 and thermoconductive insulating layer 22, which are both capable of dissipating the heat. A thin thermoconductive layer 24 may be deposited over the metal leads 14 prior to depositing at least the low-dielectric constant material 18 and the thermoconductive insulating layer 22. The low-dielectric constant material 18 has a dielectric constant of less than 3.5. An advantage of the invention is to improve reliability of metal leads for circuits using low-dielectric constant materials.Type: GrantFiled: May 31, 1994Date of Patent: December 19, 1995Assignee: Texas Instruments IncorporatedInventor: Ken Numata