Patents by Inventor Ken Okutani

Ken Okutani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070182312
    Abstract: In order too control the non-uniformity of electron emission amount within the surface or between adjacent pixels which is a cause for formation non-uniformity when forming, using anodization, an electron acceleration layer for an MIM type diode element which is appropriate for a thin film electron source, there is provided an insulation layer 12 which forms a MIM type diode element as a non-crystalline oxidized film which is formed by anodization of the surface of a lower electrode 11 with the formation of the lower electrode 11 as laminated layers which have a single layer film of aluminum or aluminum alloy or an outer layer of any of these, with a non-phosphor as a single layer film of aluminum or aluminum alloy which is anodized.
    Type: Application
    Filed: February 8, 2007
    Publication date: August 9, 2007
    Inventors: Masakazu Sagawa, Tatsumi Hirano, Hideyuki Shintani, Ken Okutani
  • Patent number: 7189636
    Abstract: A low resistance Co silicide layer with less leakage current is formed over the surface of the source and drain of a MISFET by optimizing the film forming conditions and annealing conditions upon formation of Co (cobalt) silicide. More specifically, a low resistance source and drain (n+ type semiconductor regions, p+ type semiconductor regions) with less junction leakage current are formed, upon formation of a Co silicide layer by heat treating a Co film deposited over the source and drain (n+ type semiconductor regions, p+ type semiconductor regions) of the MISFET, by depositing the Co film at a temperature as low as 200° C. or less, carrying out heat treatment in three stages to convert the Co silicide layer from a dicobalt silicide (Co2Si) layer to a cobalt monosilicide (CoSi) layer and, then, to a cobalt disilicide (CoSi2) layer, successively.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: March 13, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Kazuhito Ichinose, Hidetsugu Ogishi, Ken Okutani
  • Patent number: 7088001
    Abstract: In order to form a good contact between metallizations and improve the reliability and product yield of a semiconductor integrated circuit device, a plug is formed in a contact hole by depositing a first sputter film inside of the contact hole by traditional sputtering, depositing a second sputter film over the first sputter film by long throw sputtering, depositing a W film over the second sputtering film by CVD and removing the first and second sputter films and the W film from the outside of the contact hole. The barrier properties can be improved by constituting a barrier film from the first sputter film and second sputter film which are different in directivity.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: August 8, 2006
    Assignees: Hitachi, Ltd., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Hiroshi Ashihara, Tatsuyuki Saito, Uitsu Tanaka, Hidenori Suzuki, Hideaki Tsugane, Yasuko Yoshida, Ken Okutani
  • Patent number: 6897570
    Abstract: A highly reliable semiconductor device provided herein can prevent a junction between a pad and a wire from coming off, and pads from peeling off an underlying insulating layer on the interface thereof. The semiconductor device has plugs formed in a region in which an electrode pad is formed over a substrate. The plugs protrude into the electrode pad.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: May 24, 2005
    Assignee: Renesas Technology, Corporation
    Inventors: Takashi Nakajima, Naotaka Tanaka, Yasuyuki Nakajima, Ryo Haruta, Tomoo Matsuzawa, Masashi Sahara, Ken Okutani
  • Publication number: 20040207095
    Abstract: In order to form a good contact between metallizations and improve the reliability and product yield of a semiconductor integrated circuit device, a plug is formed in a contact hole by depositing a first sputter film inside of the contact hole by traditional sputtering, depositing a second sputter film over the first sputter film by long throw sputtering, depositing a W film over the second sputtering film by CVD and removing the first and second sputter films and the W film from the outside of the contact hole. The barrier properties can be improved by constituting a barrier film from the first sputter film and second sputter film which are different in directivity.
    Type: Application
    Filed: May 13, 2004
    Publication date: October 21, 2004
    Inventors: Hiroshi Ashihara, Tatsuyuki Saito, Uitsu Tanaka, Hidenori Suzuki, Hideaki Tsugane, Yasuko Yoshida, Ken Okutani
  • Patent number: 6764945
    Abstract: In order to form a good contact between metallizations and improve the reliability and product yield of a semiconductor integrated circuit device, a plug is formed in a contact hole by depositing a first sputter film inside of the contact hole by traditional sputtering, depositing a second sputter film over the first sputter film by long throw sputtering, depositing a W film over the second sputtering film by CVD and removing the first and second sputter films and the W film from the outside of the contact hole. The barrier properties can be improved by constituting a barrier film from the first sputter film and second sputter film which are different in directivity.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: July 20, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroshi Ashihara, Tatsuyuki Saito, Uitsu Tanaka, Hidenori Suzuki, Hideaki Tsugane, Yasuko Yoshida, Ken Okutani
  • Publication number: 20040121591
    Abstract: A low resistance Co silicide layer with less leakage current is formed over the surface of the source and drain of a MISFET by optimizing the film forming conditions and annealing conditions upon formation of Co (cobalt) silicide. Described specifically, low resistance source and drain (n+ type semiconductor regions, p+ type semiconductor regions) with less junction leakage current are formed by, upon formation of a Co silicide layer by heat treating a Co film deposited over the source and drain (n+ type semiconductor regions, p+ type semiconductor regions) of the MISFET, depositing the Co film at a temperature as low as 200° C. or less, carrying out heat treatment in three stages to convert the Co silicide layer from a dicobalt silicide (CO2Si) layer to a cobalt monosilicide (CoSi) layer and then to a cobalt disilicide (CoSi2) layer successively.
    Type: Application
    Filed: December 12, 2003
    Publication date: June 24, 2004
    Inventors: Kazuhito Ichinose, Hidetsugu Ogishi, Ken Okutani
  • Publication number: 20030230809
    Abstract: A highly reliable semiconductor device provided herein can prevent a junction between a pad and a wire from coming off, and pads from peeling off an underlying insulating layer on the interface thereof. The semiconductor device has plugs formed in a region in which an electrode pad is formed over a substrate. The plugs protrude into the electrode pad.
    Type: Application
    Filed: January 9, 2003
    Publication date: December 18, 2003
    Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takashi Nakajima, Naotaka Tanaka, Yasuyuki Nakajima, Ryo Haruta, Tomoo Matsuzawa, Masashi Sahara, Ken Okutani
  • Publication number: 20020127852
    Abstract: Disclosed is a technique capable of suppressing the damage of a semiconductor manufacturing apparatus due to the breakage or the crack to the minimum by surely detecting the breakage or the crack on a part of a wafer in a semiconductor manufacturing apparatus of a multi-chamber system. An entire image of a wafer is photographed by a camera in each time when the wafer is processed, and the photographed image is processed by a discrimination unit, thereby determining the presence of the breakage or the crack on the wafer. When the breakage or the crack is detected, an error signal is transmitted from the discrimination unit to a computer that controls the semiconductor manufacturing apparatus, and the operations of the process chamber and the transport chamber used immediately before the detection of the breakage or the crack on the wafer are stopped.
    Type: Application
    Filed: March 1, 2002
    Publication date: September 12, 2002
    Inventors: Kazuya Kawakami, Yukihiro Suzuki, Ken Okutani, Susumu Kajita, Takeshi Hashimoto
  • Publication number: 20020098670
    Abstract: In order to form a good contact between metallizations and improve the reliability and product yield of a semiconductor integrated circuit device, a plug is formed in a contact hole by depositing a first sputter film inside of the contact hole by traditional sputtering, depositing a second sputter film over the first sputter film by long throw sputtering, depositing a W film over the second sputtering film by CVD and removing the first and second sputter films and the W film from the outside of the contact hole. The barrier properties can be improved by constituting a barrier film from the first sputter film and second sputter film which are different in directivity.
    Type: Application
    Filed: April 2, 2001
    Publication date: July 25, 2002
    Inventors: Hiroshi Ashihara, Tatsuyuki Saito, Uitsu Tanaka, Hidenori Suzuki, Hideaki Tsugane, Yasuko Yoshida, Ken Okutani
  • Patent number: 5135608
    Abstract: A process and apparatus for producing semiconductor integrated circuit devices wherein the dry processing and the wet processing are continuously effected for the wafers to be processed, and the wafers are transferred between these processings under a vacuum condition or in a purging gas without being allowed to come in contact with the open air, to avoid adverse effects that will be caused by the open air.
    Type: Grant
    Filed: July 10, 1990
    Date of Patent: August 4, 1992
    Assignee: Hitachi, Ltd.
    Inventor: Ken Okutani