Patents by Inventor Ken Oowada

Ken Oowada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11024393
    Abstract: An apparatus comprises a driver circuit, sense circuit, and die controller. The driver circuit supplies a pass voltage to a selected word line and unselected word lines, a sense voltage to an adjacent word line, and a bit line voltage to bit lines coupled to selected and unselected word lines. The sense circuit determines nonconducting and conducting memory cells on the adjacent word line. The die controller then directs the driver circuit to ramp the sense voltage on the adjacent word line to the pass voltage and ramp the pass voltage on the selected word line to ground. The die controller then directs the driver circuit to ramp the bit line voltage for bit lines coupled to nonconducting memory cells to a bit line compensation voltage and directs the sense circuit to read memory cells of the selected word line based on the bit line compensation voltage.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: June 1, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Zhiping Zhang, Huai-Yuan Tseng, Ken Oowada, Deepanshu Dutta
  • Publication number: 20210142841
    Abstract: A three-dimensional (3D) memory is provided, including a memory array chip and a complementary metal-oxide semiconductor (CMOS) chip disposed on the memory array chip. The memory chip provides double write/read throughput and includes a lower region with a lower array of memory cells, lower word lines, and a lower bit line, while an upper region includes an upper array of memory cells, upper word lines, and an upper bit line. A source line is disposed between the lower and upper regions and is connected to both the lower array of memory cells and the upper array of memory cells.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 13, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Masatoshi Nishikawa, Hardwell Chibvongodze, Ken Oowada
  • Patent number: 11004525
    Abstract: Systems and methods for increasing cycling endurance and minimizing over programming of non-volatile memory cells by modulating the programming voltage applied to the non-volatile memory cells over time as the number of program/erase cycles increases are described. A bit count ratio based on bit counts within two threshold voltage zones may be used to determine the amount of voltage reduction in the programming voltage applied during subsequent programming operations. For example, if the bit count ratio is between 0.02 and 0.05, then the reduction in the programming voltage may be 100 mV; if the bit count ratio is between 0.05 and 0.10, then the reduction in the programming voltage may be 200 mV. The modulation (e.g., the reduction) of the programming voltage may be performed at varying cycle intervals depending on the total number of program/erase cycles for a memory block and/or the bit count ratio.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: May 11, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rajdeep Gautam, Ken Oowada
  • Patent number: 11004518
    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 11, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kiyohiko Sakakibara, Hiroki Yabe, Ken Oowada, Masaaki Higashitani
  • Publication number: 20210125643
    Abstract: Methods for reducing manufacturing cost and improving the reliability of non-volatile memories using NAND strings with polysilicon channels and p-type doped source lines are described. A NAND string may include a polysilicon channel that is orthogonal to a substrate and connects to a boron doped source line at a source-side end of the NAND string. To reduce the likelihood of the polysilicon channel being cut-off or pinched near the source-side end of the NAND string, a thicker polysilicon channel may be formed near the source-side end of the NAND string while a thinner polysilicon channel may be formed for the remainder of the NAND string by diffusing boron into a first portion of the polysilicon channel corresponding with the thicker polysilicon channel and then etching the polysilicon channel with etchants that exhibit a reduction in their etch rate at a boron concentration above a threshold concentration.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Kiyohiko Sakakibara, Ken Oowada
  • Patent number: 10978156
    Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 13, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Aaron Lee, Gerrit Jan Hemink, Ken Oowada, Toru Miwa
  • Patent number: 10978152
    Abstract: Systems and methods for reducing program disturb when programming portions of a memory array are described. A memory array may include a first set of NAND strings and a second set of NAND strings that share a common bit line that is connected to the drain-side end of drain-side select gates of the NAND strings and/or share a common source-side select gate line that connects to the gates of source-side select gates of the NAND strings. During programming of the first set of NAND strings a first pass voltage (e.g., 7V) may be applied to unselected word lines of the memory array and subsequently during programming of the second set of NAND strings a second pass voltage (e.g., 9V) greater than the first pass voltage may be applied to the unselected word lines of the memory array.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 13, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rajdeep Gautam, Hardwell Chibvongodze, Ken Oowada
  • Patent number: 10971231
    Abstract: Systems and methods for reducing program disturb when programming portions of a memory array are described. A memory array may include a first set of NAND strings and a second set of NAND strings that share a common bit line that is connected to the drain-side end of drain-side select gates of the NAND strings and/or share a common source-side select gate line that connects to the gates of source-side select gates of the NAND strings. During programming of the first set of NAND strings a first pass voltage (e.g., 7V) may be applied to unselected word lines of the memory array and subsequently during programming of the second set of NAND strings a second pass voltage (e.g., 9V) greater than the first pass voltage may be applied to the unselected word lines of the memory array.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 6, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rajdeep Gautam, Hardwell Chibvongodze, Ken Oowada
  • Patent number: 10957401
    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: March 23, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
  • Patent number: 10950311
    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 16, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
  • Publication number: 20200411113
    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Kiyohiko Sakakibara, Hiroki Yabe, Ken Oowada, Masaaki Higashitani
  • Publication number: 20200411114
    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 31, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Kiyohiko Sakakibara, Hiroki Yabe, Ken Oowada, Masaaki Higashitani
  • Publication number: 20200411115
    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 31, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
  • Publication number: 20200411112
    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
  • Publication number: 20200335518
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 22, 2020
    Inventors: Zhixin Cui, Masatoshi Nishikawa, Ken Oowada
  • Patent number: 10756106
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing word lines and drain select gate electrodes located over a substrate, and memory stack structures containing a respective vertical semiconductor channel and a memory film including a tunneling dielectric and a charge storage layer. A first portion of a first charge storage layer located in a first memory stack structure at level of a first drain select gate electrode is thicker than a first portion of a second charge storage layer located in a second memory stack structure at the level of the first drain select electrode.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 25, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Michiaki Sano, Ken Oowada, Zhixin Cui
  • Patent number: 10741579
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: August 11, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Masatoshi Nishikawa, Ken Oowada
  • Publication number: 20200185405
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 11, 2020
    Inventors: Zhixin CUI, Masatoshi NISHIKAWA, Ken OOWADA
  • Publication number: 20200168623
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing word lines and drain select gate electrodes located over a substrate, and memory stack structures containing a respective vertical semiconductor channel and a memory film including a tunneling dielectric and a charge storage layer. A first portion of a first charge storage layer located in a first memory stack structure at level of a first drain select gate electrode is thicker than a first portion of a second charge storage layer located in a second memory stack structure at the level of the first drain select electrode.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Inventors: Masatoshi NISHIKAWA, Michiaki SANO, Ken OOWADA, Zhixin CUI
  • Publication number: 20200005871
    Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang YANG, Aaron LEE, Gerrit Jan HEMINK, Ken OOWADA, Toru MIWA