Patents by Inventor Ken Rafftesaeth

Ken Rafftesaeth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Etch resistant shallow trench isolation in a semiconductor wafer
    Patent number: 6586814
    Abstract: A shallow isolating trench is formed in a semiconductor wafer between active component areas to electrically isolate the active components from each other. The isolating trench is primarily formed of an insulating material, such as an oxide, in a recess formed into the wafer. An etch resistant material, such as BTBAS nitride, is placed over the insulating material in the recess. The etch resistant material protects the insulating material from erosion due to subsequent semiconductor fabrication process steps, so the integrity of the isolating trench and the planarity of the wafer are generally maintained.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: July 1, 2003
    Assignee: LSI Logic Corporation
    Inventors: Rajiv Patel, David Chan, Arvind Kamath, Ken Rafftesaeth, Venkatesh P. Gopinath