Abstract: Clock pulses from a master oscillator are distributed in a multiprocessor computer system so that they arrive at a large number of utilization points located in operating clusters of modules within extremely tight time tolerances of each other. The delays associated with each component, electrical or optical connection, cable or the like are determined by direct measurement or by using known standard characteristics. A time delay budget for each complete clock pulse path from the point of initial divergence from the master clock source to the final chip delivery point is logged and summed. Components capable of introducing predetermined amounts of time delay are incorporated in some or all clock pulse paths. These components are adjusted so as to balance out the differences determined from the clock path budgets. The clock paths are implemented in electrical components either alone or in combination with optical components, or in substantially all optical configurations.

Abstract: A pin-shaped handheld test probe particularly adapted to current mode logic levels indicates through a plurality of visual indicators HIGH, LOW, MIDRANGE, OPEN and SUPPLY VOLTAGE logic levels. Each visual indicator is controlled by the output of at least one comparator amplifier having one of two inputs resistively connected to a testing point and the other input resistively coupled to a stable reference voltage level generated by a zener stabilized precision resistor ladder network. The testing point is voltage biased to give an indication of OPEN when the test probe is attached to a pin or point which is unconnected.