Patents by Inventor Ken Shiraishi
Ken Shiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8619815Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.Type: GrantFiled: January 31, 2011Date of Patent: December 31, 2013Assignee: Juniper Networks, Inc.Inventors: Souichi Kataoka, Ken Shiraishi
-
Publication number: 20110122875Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.Type: ApplicationFiled: January 31, 2011Publication date: May 26, 2011Applicant: JUNIPER NETWORKS, INC.Inventors: Souichi KATAOKA, Ken SHIRAISHI
-
Patent number: 7903668Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.Type: GrantFiled: September 30, 2009Date of Patent: March 8, 2011Assignee: Juniper Networks, Inc.Inventors: Souichi Kataoka, Ken Shiraishi
-
Publication number: 20100172248Abstract: A repeating apparatus to which a supervisory/control apparatus is connected inserts a supervisory/control signal for use by the supervisory/control apparatus to supervise or control the repeating apparatus to which the supervisory/control apparatus is not connected into an unused area within a transmission frame, and a supervisory/control unit of the repeating apparatus to which the supervisory/control apparatus is not connected extracts the supervisory/control signal from the transmission frame and outputs the extracted signal to the supervisory/control apparatus.Type: ApplicationFiled: March 18, 2009Publication date: July 8, 2010Inventor: KEN SHIRAISHI
-
Patent number: 7710980Abstract: Upon receipt of a synchronization request from the CPU, the AAL1 device of the act system causes its cell forming section to extract the allocation position information for the SAR-PDU payload about a particular time slot in the current frame and, via the synchronization information send/receive section, transfers the information to the AAL1 device of the standby system. The AAL1 device of the standby system causes its operation processing section to calculate the allocation position of a particular time slot in the next frame for the SAR-PDU payload based on the above allocation position information. The AAL1 device of the standby system starts allocation of the data of and following a particular time slot of the next frame to the SAR-PDU payload starting from the position indicated by the calculation result.Type: GrantFiled: August 20, 2007Date of Patent: May 4, 2010Assignee: Juniper Networks, Inc.Inventors: Tomoharu Shimanuki, Ken Shiraishi
-
Publication number: 20100021158Abstract: A subscriber terminating unit includes an error count counting portion counting an error count in a predetermined time range based on the number of corrections by an error correction function and an error count transmitting portion transmitting the error count to an office terminating unit. The office terminating unit includes an error count receiving portion receiving the error count from the subscriber terminating unit as a received error count and a correction method determining portion determining, based on the received error count, an error correction method or an error correction disuse which is used in the subscriber terminating unit.Type: ApplicationFiled: July 22, 2009Publication date: January 28, 2010Inventors: YOSHINORI KANNO, Ken Shiraishi, Sadaichiro Ogushi
-
Publication number: 20100020804Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.Type: ApplicationFiled: September 30, 2009Publication date: January 28, 2010Applicant: JUNIPER NETWORKS, INC.Inventors: Souichi KATAOKA, Ken SHIRAISHI
-
Patent number: 7616641Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.Type: GrantFiled: October 3, 2005Date of Patent: November 10, 2009Assignee: Juniper Networks, Inc.Inventors: Souichi Kataoka, Ken Shiraishi
-
Patent number: 7613194Abstract: A system to convert first data signals into second data signals is provided. The first system may receive one of the first data signals associated with a data frame, determine first synchronization information corresponding to one of the second data signals associated with the data frame, and output the first synchronization information. The second system may receive the first synchronization information from the first system, determine second synchronization information corresponding to another one of the second data signals associated with a subsequent data frame based on the first synchronization information, and allocate a position in the subsequent data frame based on the second synchronization information.Type: GrantFiled: April 24, 2006Date of Patent: November 3, 2009Assignee: Juniper Networks, Inc.Inventors: Tomoharu Shimanuki, Ken Shiraishi
-
Publication number: 20090232504Abstract: A plurality of lines which differ in transmission rate can coexist using a time division multiplexing (TDM) technique without any signal collision. An optical line termination (OLT) is connected to a plurality of lines which differ in transmission rate, and includes a timing extraction unit which extracts data transmission timing from a predetermined one of the plurality of lines and a timing allocation unit which allocates data transmission timing for a different line not to collide with the data transmission timing extracted by the timing extraction unit. An optical network unit (ONU) corresponding to the different line transmits data based on the allocated data transmission timing.Type: ApplicationFiled: March 12, 2009Publication date: September 17, 2009Inventor: KEN SHIRAISHI
-
Publication number: 20080043753Abstract: Upon receipt of a synchronization request from the CPU, the AAL1 device of the act system causes its cell forming section to extract the allocation position information for the SAR-PDU payload about a particular time slot in the current frame and, via the synchronization information send/receive section, transfers the information to the AAL1 device of the standby system. The AAL1 device of the standby system causes its operation processing section to calculate the allocation position of a particular time slot in the next frame for the SAR-PDU payload based on the above allocation position information. The AAL1 device of the standby system starts allocation of the data of and following a particular time slot of the next frame to the SAR-PDU payload starting from the position indicated by the calculation result.Type: ApplicationFiled: August 20, 2007Publication date: February 21, 2008Applicant: Juniper Networks, Inc.Inventors: Tomoharu Shimanuki, Ken Shiraishi
-
Publication number: 20060193326Abstract: Upon receipt of a synchronization request from the CPU, the AAL1 device of the act system causes its cell forming section to extract the allocation position information for the SAR-PDU payload about a particular time slot in the current frame and, via the synchronization information send/receive section, transfers the information to the AAL1 device of the standby system. The AAL1 device of the standby system causes its operation processing section to calculate the allocation position of a particular time slot in the next frame for the SAR-PDU payload based on the above allocation position information. The AAL1 device of the standby system starts allocation of the data of and following a particular time slot of the next frame to the SAR-PDU payload starting from the position indicated by the calculation result.Type: ApplicationFiled: April 24, 2006Publication date: August 31, 2006Applicant: Juniper Networks, Inc.Inventors: Tomoharu Shimanuki, Ken Shiraishi
-
Patent number: 7061922Abstract: Upon receipt of a synchronization request from the CPU, the AAL1 device of the act system causes its cell forming section to extract the allocation position information for the SAR-PDU payload about a particular time slot in the current frame and, via the synchronization information send/receive section, transfers the information to the AAL1 device of the standby system. The AAL1 device of the standby system causes its operation processing section to calculate the allocation position of a particular time slot in the next frame for the SAR-PDU payload based on the above allocation position information. The AAL1 device of the standby system starts allocation of the data of and following a particular time slot of the next frame to the SAR-PDU payload starting from the position indicated by the calculation result.Type: GrantFiled: March 4, 2005Date of Patent: June 13, 2006Assignee: Juniper Networks, Inc.Inventors: Tomoharu Shimanuki, Ken Shiraishi
-
Publication number: 20060077982Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.Type: ApplicationFiled: October 3, 2005Publication date: April 13, 2006Inventors: Souichi Kataoka, Ken Shiraishi
-
Patent number: 7002969Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.Type: GrantFiled: May 30, 2001Date of Patent: February 21, 2006Assignee: Juniper Networks, Inc.Inventors: Souichi Kataoka, Ken Shiraishi
-
Publication number: 20050201389Abstract: Upon receipt of a synchronization request from the CPU, the AAL1 device of the act system causes its cell forming section to extract the allocation position information for the SAR-PDU payload about a particular time slot in the current frame and, via the synchronization information send/receive section, transfers the information to the AAL1 device of the standby system. The AAL1 device of the standby system causes its operation processing section to calculate the allocation position of a particular time slot in the next frame for the SAR-PDU payload based on the above allocation position information. The AAL1 device of the standby system starts allocation of the data of and following a particular time slot of the next frame to the SAR-PDU payload starting from the position indicated by the calculation result.Type: ApplicationFiled: March 4, 2005Publication date: September 15, 2005Inventors: Tomoharu Shimanuki, Ken Shiraishi
-
Patent number: 6882650Abstract: Upon receipt of a synchronization request from the CPU, the AAL1 device of the act system causes its cell forming section to extract the allocation position information for the SAR-PDU payload about a particular time slot in the current frame and, via the synchronization information send/receive section, transfers the information to the AAL1 device of the standby system. The AAL1 device of the standby system causes its operation processing section to calculate the allocation position of a particular time slot in the next frame for the SAR-PDU payload based on the above allocation position information. The AAL1 device of the standby system starts allocation of the data of and following a particular time slot of the next frame to the SAR-PDU payload starting from the position indicated by the calculation result.Type: GrantFiled: May 17, 2001Date of Patent: April 19, 2005Assignee: Juniper Networks, Inc.Inventors: Tomoharu Shimanuki, Ken Shiraishi
-
Publication number: 20020015411Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.Type: ApplicationFiled: May 30, 2001Publication date: February 7, 2002Applicant: NEC CorporationInventors: Souichi Kataoka, Ken Shiraishi
-
Publication number: 20010043596Abstract: Upon receipt of a synchronization request from the CPU, the AAL1 device of the act system causes its cell forming section to extract the allocation position information for the SAR-PDU payload about a particular time slot in the current frame and, via the synchronization information send/receive section, transfers the information to the AAL1 device of the standby system. The AAL1 device of the standby system causes its operation processing section to calculate the allocation position of a particular time slot in the next frame for the SAR-PDU payload based on the above allocation position information. The AAL1 device of the standby system starts allocation of the data of and following a particular time slot of the next frame to the SAR-PDU payload starting from the position indicated by the calculation result.Type: ApplicationFiled: May 17, 2001Publication date: November 22, 2001Applicant: NEC CorporationInventors: Tomoharu Shimanuki, Ken Shiraishi