Patents by Inventor Ken Shiraishi

Ken Shiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8619815
    Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: December 31, 2013
    Assignee: Juniper Networks, Inc.
    Inventors: Souichi Kataoka, Ken Shiraishi
  • Publication number: 20110122875
    Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.
    Type: Application
    Filed: January 31, 2011
    Publication date: May 26, 2011
    Applicant: JUNIPER NETWORKS, INC.
    Inventors: Souichi KATAOKA, Ken SHIRAISHI
  • Patent number: 7903668
    Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: March 8, 2011
    Assignee: Juniper Networks, Inc.
    Inventors: Souichi Kataoka, Ken Shiraishi
  • Publication number: 20100172248
    Abstract: A repeating apparatus to which a supervisory/control apparatus is connected inserts a supervisory/control signal for use by the supervisory/control apparatus to supervise or control the repeating apparatus to which the supervisory/control apparatus is not connected into an unused area within a transmission frame, and a supervisory/control unit of the repeating apparatus to which the supervisory/control apparatus is not connected extracts the supervisory/control signal from the transmission frame and outputs the extracted signal to the supervisory/control apparatus.
    Type: Application
    Filed: March 18, 2009
    Publication date: July 8, 2010
    Inventor: KEN SHIRAISHI
  • Patent number: 7710980
    Abstract: Upon receipt of a synchronization request from the CPU, the AAL1 device of the act system causes its cell forming section to extract the allocation position information for the SAR-PDU payload about a particular time slot in the current frame and, via the synchronization information send/receive section, transfers the information to the AAL1 device of the standby system. The AAL1 device of the standby system causes its operation processing section to calculate the allocation position of a particular time slot in the next frame for the SAR-PDU payload based on the above allocation position information. The AAL1 device of the standby system starts allocation of the data of and following a particular time slot of the next frame to the SAR-PDU payload starting from the position indicated by the calculation result.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: May 4, 2010
    Assignee: Juniper Networks, Inc.
    Inventors: Tomoharu Shimanuki, Ken Shiraishi
  • Publication number: 20100021158
    Abstract: A subscriber terminating unit includes an error count counting portion counting an error count in a predetermined time range based on the number of corrections by an error correction function and an error count transmitting portion transmitting the error count to an office terminating unit. The office terminating unit includes an error count receiving portion receiving the error count from the subscriber terminating unit as a received error count and a correction method determining portion determining, based on the received error count, an error correction method or an error correction disuse which is used in the subscriber terminating unit.
    Type: Application
    Filed: July 22, 2009
    Publication date: January 28, 2010
    Inventors: YOSHINORI KANNO, Ken Shiraishi, Sadaichiro Ogushi
  • Publication number: 20100020804
    Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.
    Type: Application
    Filed: September 30, 2009
    Publication date: January 28, 2010
    Applicant: JUNIPER NETWORKS, INC.
    Inventors: Souichi KATAOKA, Ken SHIRAISHI
  • Patent number: 7616641
    Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: November 10, 2009
    Assignee: Juniper Networks, Inc.
    Inventors: Souichi Kataoka, Ken Shiraishi
  • Patent number: 7613194
    Abstract: A system to convert first data signals into second data signals is provided. The first system may receive one of the first data signals associated with a data frame, determine first synchronization information corresponding to one of the second data signals associated with the data frame, and output the first synchronization information. The second system may receive the first synchronization information from the first system, determine second synchronization information corresponding to another one of the second data signals associated with a subsequent data frame based on the first synchronization information, and allocate a position in the subsequent data frame based on the second synchronization information.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: November 3, 2009
    Assignee: Juniper Networks, Inc.
    Inventors: Tomoharu Shimanuki, Ken Shiraishi
  • Publication number: 20090232504
    Abstract: A plurality of lines which differ in transmission rate can coexist using a time division multiplexing (TDM) technique without any signal collision. An optical line termination (OLT) is connected to a plurality of lines which differ in transmission rate, and includes a timing extraction unit which extracts data transmission timing from a predetermined one of the plurality of lines and a timing allocation unit which allocates data transmission timing for a different line not to collide with the data transmission timing extracted by the timing extraction unit. An optical network unit (ONU) corresponding to the different line transmits data based on the allocated data transmission timing.
    Type: Application
    Filed: March 12, 2009
    Publication date: September 17, 2009
    Inventor: KEN SHIRAISHI
  • Publication number: 20080043753
    Abstract: Upon receipt of a synchronization request from the CPU, the AAL1 device of the act system causes its cell forming section to extract the allocation position information for the SAR-PDU payload about a particular time slot in the current frame and, via the synchronization information send/receive section, transfers the information to the AAL1 device of the standby system. The AAL1 device of the standby system causes its operation processing section to calculate the allocation position of a particular time slot in the next frame for the SAR-PDU payload based on the above allocation position information. The AAL1 device of the standby system starts allocation of the data of and following a particular time slot of the next frame to the SAR-PDU payload starting from the position indicated by the calculation result.
    Type: Application
    Filed: August 20, 2007
    Publication date: February 21, 2008
    Applicant: Juniper Networks, Inc.
    Inventors: Tomoharu Shimanuki, Ken Shiraishi
  • Publication number: 20060193326
    Abstract: Upon receipt of a synchronization request from the CPU, the AAL1 device of the act system causes its cell forming section to extract the allocation position information for the SAR-PDU payload about a particular time slot in the current frame and, via the synchronization information send/receive section, transfers the information to the AAL1 device of the standby system. The AAL1 device of the standby system causes its operation processing section to calculate the allocation position of a particular time slot in the next frame for the SAR-PDU payload based on the above allocation position information. The AAL1 device of the standby system starts allocation of the data of and following a particular time slot of the next frame to the SAR-PDU payload starting from the position indicated by the calculation result.
    Type: Application
    Filed: April 24, 2006
    Publication date: August 31, 2006
    Applicant: Juniper Networks, Inc.
    Inventors: Tomoharu Shimanuki, Ken Shiraishi
  • Patent number: 7061922
    Abstract: Upon receipt of a synchronization request from the CPU, the AAL1 device of the act system causes its cell forming section to extract the allocation position information for the SAR-PDU payload about a particular time slot in the current frame and, via the synchronization information send/receive section, transfers the information to the AAL1 device of the standby system. The AAL1 device of the standby system causes its operation processing section to calculate the allocation position of a particular time slot in the next frame for the SAR-PDU payload based on the above allocation position information. The AAL1 device of the standby system starts allocation of the data of and following a particular time slot of the next frame to the SAR-PDU payload starting from the position indicated by the calculation result.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: June 13, 2006
    Assignee: Juniper Networks, Inc.
    Inventors: Tomoharu Shimanuki, Ken Shiraishi
  • Publication number: 20060077982
    Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.
    Type: Application
    Filed: October 3, 2005
    Publication date: April 13, 2006
    Inventors: Souichi Kataoka, Ken Shiraishi
  • Patent number: 7002969
    Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: February 21, 2006
    Assignee: Juniper Networks, Inc.
    Inventors: Souichi Kataoka, Ken Shiraishi
  • Publication number: 20050201389
    Abstract: Upon receipt of a synchronization request from the CPU, the AAL1 device of the act system causes its cell forming section to extract the allocation position information for the SAR-PDU payload about a particular time slot in the current frame and, via the synchronization information send/receive section, transfers the information to the AAL1 device of the standby system. The AAL1 device of the standby system causes its operation processing section to calculate the allocation position of a particular time slot in the next frame for the SAR-PDU payload based on the above allocation position information. The AAL1 device of the standby system starts allocation of the data of and following a particular time slot of the next frame to the SAR-PDU payload starting from the position indicated by the calculation result.
    Type: Application
    Filed: March 4, 2005
    Publication date: September 15, 2005
    Inventors: Tomoharu Shimanuki, Ken Shiraishi
  • Patent number: 6882650
    Abstract: Upon receipt of a synchronization request from the CPU, the AAL1 device of the act system causes its cell forming section to extract the allocation position information for the SAR-PDU payload about a particular time slot in the current frame and, via the synchronization information send/receive section, transfers the information to the AAL1 device of the standby system. The AAL1 device of the standby system causes its operation processing section to calculate the allocation position of a particular time slot in the next frame for the SAR-PDU payload based on the above allocation position information. The AAL1 device of the standby system starts allocation of the data of and following a particular time slot of the next frame to the SAR-PDU payload starting from the position indicated by the calculation result.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: April 19, 2005
    Assignee: Juniper Networks, Inc.
    Inventors: Tomoharu Shimanuki, Ken Shiraishi
  • Publication number: 20020015411
    Abstract: A circuit simulation apparatus is disclosed by which, even if an STS-N frame of an abnormal length is detected by a reassembly buffer, the frame length can be compensated for while preventing an overflow of the reassembly buffer. When an STS-(N×M) frame formed by multiplexing M STS-N frames formed from different channels is cellularized into ATM cells or M different STS-N frames assembled from ATM cells are multiplexed into an STS-(N×M) frame, an ATM cell sync signal and ATM cell data from a buffer section are outputted as a frame pulse signal and frame data from a reassembly section to a circuit termination section, and frame length compensation of the frame pulse signal and the frame data is performed by the reassembly section.
    Type: Application
    Filed: May 30, 2001
    Publication date: February 7, 2002
    Applicant: NEC Corporation
    Inventors: Souichi Kataoka, Ken Shiraishi
  • Publication number: 20010043596
    Abstract: Upon receipt of a synchronization request from the CPU, the AAL1 device of the act system causes its cell forming section to extract the allocation position information for the SAR-PDU payload about a particular time slot in the current frame and, via the synchronization information send/receive section, transfers the information to the AAL1 device of the standby system. The AAL1 device of the standby system causes its operation processing section to calculate the allocation position of a particular time slot in the next frame for the SAR-PDU payload based on the above allocation position information. The AAL1 device of the standby system starts allocation of the data of and following a particular time slot of the next frame to the SAR-PDU payload starting from the position indicated by the calculation result.
    Type: Application
    Filed: May 17, 2001
    Publication date: November 22, 2001
    Applicant: NEC Corporation
    Inventors: Tomoharu Shimanuki, Ken Shiraishi