Abstract: A computer system and associated docking station couple via PCI bus signals and sideband signals using a hot pluggable serial bus between a pair of PCI bridges, one bridge located in the computer, and one bridge located in the dock. The hot pluggable bus preferably comprises an IEEE 1394 serial bus. Each bridge captures the state of the PCI bus during selected PCI cycles and transmits the bus values to the other bridge over the IEEE 1394 bus. The bridge that receives the PCI values drives its own PCI bus with the values captured on the other PCI bus, thus performing the duties of a conventional PCI-to-PCI bridge. The docking bridges exchange sideband signals in a similar manner over the IEEE 1394 bus.

Abstract: A hot dockable computer system comprises an enhanced expansion bus bridge for coupling the computer system to a docking station. The enhanced bus bridge includes an ACPI control unit for controlling the power state of the bridge device and associated buses. The ACPI control unit receives a docking signal from a docking connector on the computer that is asserted to indicate when a docking sequence has completed. When the docking signal is asserted, the bus bridge transmits a PME interrupt to the operating system, which activates the bus bridge. The bus bridge further includes a plurality of switches coupling the expansion bus signals in the computer system to the expansion bus signals in the dock. The ACPI control unit opens the switches when the bus bridge is deactivated, decoupling the expansion bus in the computer from the expansion bus in the dock. Similarly, the ACPI control unit deasserts the control signal to close the switches when the bus bridge is activated, connecting the expansion buses.

Abstract: A PCI bus controller which operates according to the PCI clock run protocol, without the complexity of a typical PCI bridge. This provides the power savings of Mobile PCI Clock run without the overhead, cost and complexity of a PCI to PCI bridge. This is accomplished by supplying a clock run controller, which sits on between the upstream PCI bus and a downstream PCI device, monitors traffic on the bus to determine if the PCI device is being actively accessed. If not, the clock to the PCI device is controlled according to the clock run protocol.