Abstract: A scan-type display device control circuit is suitable for receiving successive frame data and driving a light-emitting diode (LED) display device accordingly. The scan-type display device control circuit includes a ping-pong buffer, a data storage controller, a line scan controller, a display buffer, and a scrambled pulse width modulation (PMW) signal generating device. The scan-type display device control circuit can utilize frame data circularly and repeatedly, so as to prevent a great mass of data from being transmitted repeatedly. Therefore, a band width for inputting data can be reduced significantly. Furthermore, the scrambled PMW signal generating device can scramble a PMW signal with a long period into a plurality of scrambled PMW signals with a short period. Therefore, the refresh rate can be efficiently enhanced without changing the band width for inputting data.

Abstract: A driving system and a method for a dot-matrix light-emitting diode display device. The driving system comprises a controller, a scan line driver, and a signal line driver. The controller provides a scan line control signal and a signal line control signal. The scan line driver generates a scan line driving signal in response to the scan line control signal. The scan line driving signal is divided into an ON period and a OFF period. The signal line driver generates a signal line driving signal in response to the signal line control signal. The signal line driver generates a discharging control signal or a charging control signal during the OFF period so that the signal line driver and the plurality of signal lines form the discharging or charging paths. Therefore, the parasitic capacitors on the scan lines are discharged or the parasitic capacitors on the signal lines are charged.

Abstract: A serial controller is adapted to receive an external clock and an input data, and output an inverted clock and an output data. The serial controller includes an inverter, a serial position detector, a synchronous clock generator, a serial register, and a half-cycle delay unit. Thereby, through the serial controller, the problem that the data signal and the driving clock are not synchronous when the clock series are inverted is avoided. Besides, a bi-directional serial controller further includes an identification unit and a data directing unit, and the serial controller is enabled to return the current status to a central control unit to serve as the reference for error detection.

Abstract: A serial controller is adapted to receive an external clock and an input data, and output an inverted clock and an output data. The serial controller includes an inverter, a serial position detector, a synchronous clock generator, a serial register, and a half-cycle delay unit. Thereby, through the serial controller, the problem that the data signal and the driving clock are not synchronous when the clock series are inverted is avoided. Besides, a bi-directional serial controller further includes an identification unit and a data directing unit, and the serial controller is enabled to return the current status to a central control unit to serve as the reference for error detection.

Abstract: A scan-type display device control circuit is suitable for receiving successive frame data and driving a light-emitting diode (LED) display device accordingly. The scan-type display device control circuit includes a ping-pong buffer, a data storage controller, a line scan controller, a display buffer, and a scrambled pulse width modulation (PMW) signal generating device. The scan-type display device control circuit can utilize frame data circularly and repeatedly, so as to prevent a great mass of data from being transmitted repeatedly. Therefore, a band width for inputting data can be reduced significantly. Furthermore, the scrambled PMW signal generating device can scramble a PMW signal with a long period into a plurality of scrambled PMW signals with a short period. Therefore, the refresh rate can be efficiently enhanced without changing the band width for inputting data.

Abstract: The present invention discloses a cooperation circuit, comprising: a first control module, capable of generating a first control signal and a second control signal, the pulse width of the first control signal being determined by the pulse width of the second control signal; and a second control module, coupled to the first control module to receive the first control signal and the second control signal and generate a third control signal according to the first control signal and the second control signal; wherein, according to the first control signal and the second control signal, the second control module enables the third control signal and the second control signal to exhibit the same frequency and the same duty cycle with a phase delay.

Abstract: The present invention discloses a cooperation circuit, comprising: a first control module, capable of generating a first control signal and a second control signal, the pulse width of the first control signal being determined by the pulse width of the second control signal; and a second control module, coupled to the first control module to receive the first control signal and the second control signal and generate a third control signal according to the first control signal and the second control signal; wherein, according to the first control signal and the second control signal, the second control module enables the third control signal and the second control signal to exhibit the same frequency and the same duty cycle with a phase delay.