Patents by Inventor Ken Uchida
Ken Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096305Abstract: A vibration device includes: a glass vibration plate including a plurality of glass plates being laminated, and a solid-phase intermediate layer between at least a pair of the glass plates among the glass plates; a vibrator fixed to the glass vibration plate and configured to vibrate the glass vibration plate, in which the glass vibration plate includes a temperature adjustment unit configured to adjust a temperature of the intermediate layer.Type: ApplicationFiled: November 15, 2023Publication date: March 21, 2024Applicant: AGC Inc.Inventors: Jun AKIYAMA, Kento SAKURAI, Daisuke UCHIDA, Ken FUJITA
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Publication number: 20230288367Abstract: A detection device includes: an ion conductor; three or more electrodes that are in contact with the ion conductor; and an ammeter embodying a measurement unit that measures a potential difference between two electrodes when a fluid sample is in contact with the ion conductor or the electrode, the two electrodes being selected from the three or more electrodes in a plurality of combinations.Type: ApplicationFiled: January 30, 2023Publication date: September 14, 2023Inventors: Takahisa TANAKA, Takeaki YAJIMA, Ken UCHIDA
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Publication number: 20230174774Abstract: Provided is a resin composition, a molded body of which is an electromagnetic wave absorber. An imaginary part (??) of a complex dielectric constant at 25° C. and 10 GHz and a volume resistivity (?v) at 25° C. of the molded body satisfy the relational expression (1) below, and the imaginary part (??) is greater than 1.25.Type: ApplicationFiled: May 25, 2021Publication date: June 8, 2023Applicant: KYOCERA CORPORATIONInventors: Ken UCHIDA, Hirokazu TSURUMI
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Patent number: 11281021Abstract: To be stably wearable without nose pads and to have a support structure which is inconspicuous when worn, eyeglasses include: temples which are wide in an upward/downward direction; and temple pads each having a tip and a root, the root being fixed to a prescribed location on an inner side of a corresponding one of the temples, each of the temple pads extending along an extension direction of the corresponding one of the temples to gradually deviates from an inner side surface of the corresponding one of the temples from the prescribed location to the tip, each of the temple pads has a root portion which is narrow and a tip portion formed to have a thick shape that gently protrudes downward, the tip portion being in contact with a wearer's temple when the eyeglasses are worn, the temple pads being entirely or mostly hidden by the temples in a side view.Type: GrantFiled: November 29, 2019Date of Patent: March 22, 2022Assignee: IZONE JAPAN INC.Inventor: Ken Uchida
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Publication number: 20210311323Abstract: To be stably wearable without nose pads and to have a support structure which is inconspicuous when worn, eyeglasses include: temples which are wide in an upward/downward direction; and temple pads each having a tip and a root, the root being fixed to a prescribed location on an inner side of a corresponding one of the temples, each of the temple pads extending along an extension direction of the corresponding one of the temples to gradually deviates from an inner side surface of the corresponding one of the temples from the prescribed location to the tip, each of the temple pads has a root portion which is narrow and a tip portion formed to have a thick shape that gently protrudes downward, the tip portion being in contact with a wearer's temple when the eyeglasses are worn, the temple pads being entirely or mostly hidden by the temples in a side view.Type: ApplicationFiled: November 29, 2019Publication date: October 7, 2021Inventor: Ken UCHIDA
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Patent number: 10696840Abstract: A resin composition for semiconductor encapsulation, containing (A) an epoxy resin, (B) a phenolic resin-based curing agent, (C) an inorganic filler, and (D) amorphous carbon, wherein the amorphous carbon of the component (D) contains 30 atomic % or more of an SP3 structure and 55 atomic % or less of an SP2 structure.Type: GrantFiled: November 5, 2015Date of Patent: June 30, 2020Assignee: KYOCERA CORPORATIONInventors: Ken Uchida, Shinichi Kazama, Yoshitake Terashi
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Publication number: 20170267859Abstract: A resin composition for semiconductor encapsulation, containing (A) an epoxy resin, (B) a phenolic resin-based curing agent, (C) an inorganic filler, and (D) amorphous carbon, wherein the amorphous carbon of the component (D) contains 30 atomic % or more of an SP3 structure and 55 atomic % or less of an SP2 structure.Type: ApplicationFiled: November 5, 2015Publication date: September 21, 2017Applicant: KYOCERA CorporationInventors: Ken UCHIDA, Shinichi KAZAMA, Yoshitake TERASHI
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Patent number: 9251919Abstract: The pressurized water reactor according an embodiment comprises: a cylindrical reactor pressure vessel (1) to which inlet nozzles are connected; fuel assemblies which are contained within the reactor pressure vessel (1); a cylindrical reactor core barrel (3) which surrounds the fuel assemblies and forms an annular downcomer (6) between the reactor core barrel (3) and the inner surface of the reactor pressure vessel (1); and radial supports. The radial supports are supports which are arranged below the downcomer (6) at intervals in the circumferential direction, each has vertical flow path formed therein, and position the reactor core barrel (3) and the reactor pressure vessel (1). The radial supports each has, for example, a flow path-equipped radial keys (21) and a key groove member (40).Type: GrantFiled: December 13, 2011Date of Patent: February 2, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Chikako Iwaki, Tatsumi Ikeda, Tetsuzo Yamamoto, Masanobu Watanabe, Satoru Abe, Ken Uchida, Hisaki Sato, Ken Okuda, Kiichi Ito
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Publication number: 20140332895Abstract: A random number generation device includes: a first source region; a first drain region; a first channel region provided between the first source region and the first drain region; a first insulating film provided on the first channel region; and a first gate electrode provided on the first insulating film. The first insulating film has a trap capturing and releasing a charge, and a tensile or compressive stress is applied in a direction of a gate length to at least one of the first channel region and the first insulating film.Type: ApplicationFiled: July 29, 2014Publication date: November 13, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shigeki KOBAYASHI, Ken UCHIDA, Shinobu FUJITA, Tetsufumi TANAMOTO
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Publication number: 20140037038Abstract: A pressurized water reactor comprises a reactor pressure vessel (11), a cylindrical core barrel (13), a core disposed in the core barrel (13), a lower core support plate (17), and a cylindrical porous plate (31). The core barrel (13) is provided in the reactor pressure vessel (11) and forms, with the inner side surface of the reactor pressure vessel (11), an annular downcomer (14) therebetween. The lower core support plate (17) is provided under the core so as to extend horizontally, and a large number of upward flow holes (80) are formed therein. The cylindrical porous plate (31) demarcates a lower plenum (16) and a bottom part of the downcomer (14), and a plurality of inward flow holes (83) that serve as flow paths from the bottom part of the downcomer (14) to the lower plenum (16) are formed therein. The inward flow holes (83) are inclined upward to the lower plenum (16) on the side on which the inward flow holes are open to the lower plenum (16).Type: ApplicationFiled: January 18, 2012Publication date: February 6, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Ken Uchida, Ken Okuda, Kazuyoshi Aoki, Hiroshi Ikeda, Chikako Iwaki, Tetsuzo Yamamoto
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Publication number: 20130343505Abstract: The pressurized water reactor according an embodiment comprises: a cylindrical reactor pressure vessel (1) to which inlet nozzles are connected; fuel assemblies which are contained within the reactor pressure vessel (1); a cylindrical reactor core barrel (3) which surrounds the fuel assemblies and forms an annular downcomer (6) between the reactor core barrel (3) and the inner surface of the reactor pressure vessel (1); and radial supports. The radial supports are supports which are arranged below the downcomer (6) at intervals in the circumferential direction, each has vertical flow path formed therein, and position the reactor core barrel (3) and the reactor pressure vessel (1). The radial supports each has, for example, a flow path-equipped radial keys (21) and a key groove member (40).Type: ApplicationFiled: December 13, 2011Publication date: December 26, 2013Inventors: Chikako Iwaki, Tatsumi Ikeda, Tetsuzo Yamamoto, Masanobu Watanabe, Satoru Abe, Ken Uchida, Hisaki Sato, Ken Okuda, Kiichi Ito
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Patent number: 8399926Abstract: A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.Type: GrantFiled: October 27, 2011Date of Patent: March 19, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Masumi Saitoh, Ken Uchida
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Publication number: 20120037994Abstract: A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.Type: ApplicationFiled: October 27, 2011Publication date: February 16, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masumi SAITOH, Ken UCHIDA
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Patent number: 8076231Abstract: A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.Type: GrantFiled: March 11, 2009Date of Patent: December 13, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masumi Saitoh, Ken Uchida
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Patent number: 8039887Abstract: A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.Type: GrantFiled: May 5, 2010Date of Patent: October 18, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masumi Saitoh, Ken Uchida
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Publication number: 20100213533Abstract: A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.Type: ApplicationFiled: May 5, 2010Publication date: August 26, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Masumi SAITOH, Ken Uchida
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Patent number: 7781274Abstract: A multi-gate field effect transistor includes: a plurality of semiconductor layers arranged in parallel on a substrate; source and drain regions formed in each of the semiconductor layers; channel regions each provided between the source region and the drain region in each of the semiconductor layers; protection films each provided on an upper face of each of the channel regions; gate insulating films each provided on both side faces of each of the channel regions; a plurality of gate electrodes provided on both side faces of each of the channel regions so as to interpose the gate insulating film, provided above the upper face of each of the channel region so as to interpose the protection film, and containing a metal element; a connecting portion connecting upper faces of the gate electrodes; and a gate wire connected to the connecting portion.Type: GrantFiled: September 15, 2008Date of Patent: August 24, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yukio Nakabayashi, Ken Uchida
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Patent number: 7737486Abstract: A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.Type: GrantFiled: September 21, 2007Date of Patent: June 15, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Masumi Saitoh, Ken Uchida
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Publication number: 20090309646Abstract: A random number generation device includes: a first source region; a first drain region; a first channel region provided between the first source region and the first drain region; a first insulating film provided on the first channel region; and a first gate electrode provided on the first insulating film. The first insulating film has a trap capturing and releasing a charge, and a tensile or compressive stress is applied in a direction of a gate length to at least one of the first channel region and the first insulating film.Type: ApplicationFiled: February 24, 2009Publication date: December 17, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Shigeki KOBAYASHI, Ken Uchida, Shinobu Fujita, Tetsufumi Tanamoto
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Patent number: 7605422Abstract: A semiconductor device capable of realizing low-voltage drivability and large storage capacity (miniaturization) by achieving large threshold voltage shifts and long retention time while at the same time suppressing variations in characteristics among memory cells is disclosed. The device includes a semiconductor memory cell having a channel region formed in a semiconductor substrate, a tunnel insulator film on the channel region, a charge storage insulator film on the tunnel insulator film, a control dielectric film on the charge storage film, a control electrode on the control dielectric film, and source/drain regions at opposite ends of the channel region. The memory cell's channel region has a cross-section at right angles to a direction along the channel length, the width W and height H of which are each less than or equal to 10 nm.Type: GrantFiled: August 29, 2007Date of Patent: October 20, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Masumi Saitoh, Ken Uchida